ADSP-BF512KSWZ-3 Analog Devices Inc, ADSP-BF512KSWZ-3 Datasheet - Page 33

• Manufacturer Part Number: ADSP-BF512KSWZ-3
• Description: Low-Power Blackfin Processor
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF512KSWZ-3

• Interface: I²C, PPI, SPI, SPORT, UART/USART
• Clock Rate: 300MHz
• Non-volatile Memory: External
• On-chip Ram: 116kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.30V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP Exposed Pad, 176-eLQFP, 176-HLQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Parallel Peripheral Interface Timing
Table 30
Figure 24 on Page 40
operations.
Table 30. Parallel Peripheral Interface Timing
1
guaranteed to be received correctly by the PPI peripheral.
Parameter
Timing Requirements
t
t
Timing Requirements - GP Input and Frame Capture Modes
t
t
t
t
t
Switching Characteristics - GP Output and Frame Capture Modes
t
t
t
t
The PPI port is fully enabled 4 PPI clock cycles after the PAB write to the PPI port enable bit. Only after the PPI port is fully enabled are external frame syncs and data words
PCLKW
PCLK
PSUD
SFSPE
HFSPE
SDRPE
HDRPE
DFSPE
HOFSPE
DDTPE
HDTPE
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
and
Figure 15 on Page
PPI_CLK Width
PPI_CLK Period
External Frame Sync Startup Delay
External Frame Sync Setup Before PPI_CLK
(Nonsampling Edge for Rx, Sampling Edge for Tx)
External Frame Sync Hold After PPI_CLK
Receive Data Setup Before PPI_CLK
Receive Data Hold After PPI_CLK
Internal Frame Sync Delay After PPI_CLK
Internal Frame Sync Hold After PPI_CLK
Transmit Data Delay After PPI_CLK
Transmit Data Hold After PPI_CLK
PPI_FS1/2
PPI_DATA
PPI_CLK
describe parallel peripheral interface
PPI_FS1/2
PPI_CLK
33,
t
SFSPE
Figure 21 on Page
FRAME SYNC SAMPLED
DATA SAMPLED /
Figure 15. PPI GP Rx Mode with External Frame Sync Timing
1
Figure 14. PPI with External Frame Sync Timing
Rev. B | Page 33 of 68 | January 2011
38, and
t
HFSPE
t
SDRPE
FRAME SYNC SAMPLED
DATA SAMPLED /
t
PSUD
Min
t
2 × t
4 × t
6.7
1.75
4.1
2
1.7
2.3
SCLK
– 1.5
SCLK
PCLK
1.8 V Nominal
t
PCLKW
– 1.5
t
V
HDRPE
DDEXT
Max
8
8.2
t
PCLK
Min
t
2 × t
4 × t
6.7
1.75
3.5
1.6
1.7
1.9
SCLK
2.5 V/3.3 V Nominal
– 1.5
SCLK
PCLK
– 1.5
V
DDEXT
Max
8
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns