CY7C1061AV33-12ZXCT Cypress Semiconductor Corp, CY7C1061AV33-12ZXCT Datasheet - Page 4

• Manufacturer Part Number: CY7C1061AV33-12ZXCT
• Description: CY7C1061AV33-12ZXCT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1061AV33-12ZXCT

• Format - Memory: RAM
• Memory Type: SRAM - Asynchronous
• Memory Size: 16M (1M x 16)
• Speed: 12ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-TSOP II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-05256 Rev. *G
AC Switching Characteristics
Notes
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
7. This part has a voltage regulator that steps down the voltage from 3V to 2V internally. t
8. t
9. These parameters are guaranteed by design and are not tested.
10. The internal Write time of the memory is defined by the overlap of CE
11. The minimum Write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of t
power
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
DBE
LZBE
HZBE
WC
SCE
AW
HA
SA
PWE
SD
HD
LZWE
HZWE
BW
I
page
Transition is measured ±200 mV from steady-state voltage.
must be LOW to initiate a Write, and the transition of any of these signals can terminate the Write. The input data setup and hold timing should be referenced to
the leading edge of the signal that terminates the Write.
OL
HZOE
Parameter
/I
OH
3, unless specified otherwise.
, t
HZCE
and specified transmission line loads. Test conditions for the Read cycle use output loading shown in (a) of the
, t
[10, 11]
HZWE
, t
HZBE
V
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z
CE
CE
CE
CE
Byte Enable to Data Valid
Byte Enable to Low-Z
Byte Disable to High-Z
Write Cycle Time
CE
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE HIGH to Low-Z
WE LOW to High-Z
Byte Enable to End of Write
and t
CC
1
1
1
1
1
1
(typical) to the first access
LOW/CE
LOW/CE
HIGH/CE
LOW/CE
HIGH/CE
LOW/CE
LZOE
, t
LZCE
, t
2
2
2
2
2
2
\LZWE
HIGH to Data Valid
HIGH to Low-Z
HIGH to Power Up
HIGH to Write End
(Over the Operating Range)
LOW to High-Z
LOW to Power Down
Description
, t
[8]
[8]
[8]
LZBE
are specified with a load capacitance of 5 pF as in (b) of
[7]
[8]
[8]
1
[9]
LOW (CE
[9]
2
HIGH) and WE LOW. Chip enables must be active and WE and byte enables
[6]
power
time must be provided initially before a Read/Write operation is started.
HZWE
Min
5.5
10
10
1
3
1
3
0
1
7
7
0
0
7
0
3
7
and t
–10
SD
.
Max
10
10
10
5
5
5
5
5
5
“AC Test Loads and Waveforms
“AC Test Loads and Waveforms
Min
12
12
CY7C1061AV33
1
3
1
3
0
1
8
8
0
0
8
6
0
3
8
–12
Max
12
12
12
6
6
6
6
6
6
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[5]
” on page
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[5]
” on
3.
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