DSPIC33EP256MU810-I/PT Microchip Technology, DSPIC33EP256MU810-I/PT Datasheet - Page 388

• Manufacturer Part Number: DSPIC33EP256MU810-I/PT
• Description: 100 PINS, 256KB Flash, 28KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 12x12x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP256MU810-I/PT

• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 83
• Flash Memory Size: 280KB
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: TQFP
• No. Of Pins: 100
• Rohs Compliant: Yes
• Processor Series: DSPIC33E
• Core: dsPIC
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 256KB (85.5K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 12K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / Rohs Status: Details

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
REGISTER 23-3:
DS70616E-page 388
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-13
bit 12-11
bit 10
bit 9-8
bit 7
bit 6-2
R/W-0
BUFS
R-0
VCFG<2:0>: Converter Voltage Reference Configuration bits
Unimplemented: Read as ‘0’
CSCNA: Input Scan Select bit
1 = Scan inputs for CH0+ during Sample A bit
0 = Do not scan inputs
CHPS<1:0>: Channel Select bits
When AD12B = 1, CHPS<1:0> is: U-0, Unimplemented, Read as ‘0’
1x = Converts CH0, CH1, CH2 and CH3
01 = Converts CH0 and CH1
00 = Converts CH0
BUFS: Buffer Fill Status bit (only valid when BUFM = 1)
1 = ADC is currently filling the second half of the buffer. The user application should access data in the
0 = ADC is currently filling the first half of the buffer. The user application should access data in the
SMPI<3:0>: Increment Rate bits
When ADDMAEN = 0:
1111 = Generates interrupt after completion of every 16th sample/conversion operation
1110 = Generates interrupt after completion of every 15th sample/conversion operation
•
•
•
0001 = Generates interrupt after completion of every 2nd sample/conversion operation
0000 = Generates interrupt after completion of every sample/conversion operation
When ADDMAEN = 1:
1111 = Increments the DMA address after completion of every 16th sample/conversion operation
1110 = Increments the DMA address after completion of every 15th sample/conversion operation
•
•
•
0001 = Increments the DMA address after completion of every 2nd sample/conversion operation
0000 = Increments the DMA address after completion of every sample/conversion operation
VCFG<2:0>
000
001
010
011
1xx
R/W-0
first half of the buffer
second half of the buffer.
U-0
—
AD2CON2: ADC2 CONTROL REGISTER 2
External V
External V
W = Writable bit
‘1’ = Bit is set
V
A
A
A
REFH
R/W-0
R/W-0
VDD
VDD
VDD
REF
REF
+
+
External V
External V
R/W-0
Preliminary
U-0
—
V
Avss
Avss
Avss
REFL
SMPI<3:0>
REF
REF
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
-
-
R/W-0
U-0
—
CSCNA
R/W-0
R/W-0
 2009-2011 Microchip Technology Inc.
x = Bit is unknown
BUFM
R/W-0
R/W-0
CHPS<1:0>
R/W-0
R/W-0
ALTS
bit 8
bit 0