DSPIC33EP256MU810-I/PT Microchip Technology, DSPIC33EP256MU810-I/PT Datasheet - Page 438

• Manufacturer Part Number: DSPIC33EP256MU810-I/PT
• Description: 100 PINS, 256KB Flash, 28KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 12x12x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP256MU810-I/PT

• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 83
• Flash Memory Size: 280KB
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: TQFP
• No. Of Pins: 100
• Rohs Compliant: Yes
• Processor Series: DSPIC33E
• Core: dsPIC
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 256KB (85.5K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 12K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / Rohs Status: Details

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
TABLE 29-2:
DS70616E-page 438
Note 1:
POSCMD<1:0>
FNOSC<2:0>
FCKSM<1:0>
GSSK<1:0>
OSCIOFNC
IOL1WAY
FWDTEN
Bit Field
WINDIS
GWRP
IESO
GSS
2:
This bit is not available on dsPIC33EP256MU806 (64-pin) devices.
BOR should always be enabled for proper operation (BOREN = 1).
CONFIGURATION BITS DESCRIPTION
FOSCSEL
FOSCSEL
Register
FWDT
FWDT
FOSC
FOSC
FOSC
FOSC
FGS
FGS
FGS
is enabled, the
RTSP effect is
If clock switch
on any device
RTSP Effect
Immediate
Immediate
Immediate
Immediate
Immediate
Immediate
Immediate
Immediate
Immediate
Immediate
otherwise,
immediate
Reset;
General Segment Key bits.
These bits must be set to ‘00’ if GWRP = 1 and GSS = 1.
These bits must be set to ‘11’ for any other value of the GWRP and
GSS bits.
Any mismatch between either the GWRP or GSS bits, and the
GSSK bits (as described above), will result in code protection
getting enabled for the General Segment. A Flash bulk erase will be
required to unlock the device.
General Segment Code-Protect bit
1 = User program memory is not code-protected
0 = User program memory is code-protected
General Segment Write-Protect bit
1 = User program memory is not write-protected
0 = User program memory is write-protected
Two-speed Oscillator Start-up Enable bit
1 = Start-up device with FRC, then automatically switch to the
0 = Start-up device with user-selected oscillator source
Initial Oscillator Source Selection bits
111 = Internal Fast RC (FRC) Oscillator with postscaler
110 = Internal Fast RC (FRC) Oscillator with divide-by-16
101 = LPRC Oscillator
100 = Secondary (LP) Oscillator
011 = Primary (XT, HS, EC) Oscillator with PLL
010 = Primary (XT, HS, EC) Oscillator
001 = Internal Fast RC (FRC) Oscillator with PLL
000 = FRC Oscillator
Clock Switching Mode bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
Peripheral pin select configuration
1 = Allow only one reconfiguration
0 = Allow multiple reconfigurations
OSC2 Pin Function bit (except in XT and HS modes)
1 = OSC2 is clock output
0 = OSC2 is general purpose digital I/O pin
Primary Oscillator Mode Select bits
11 = Primary Oscillator disabled
10 = HS Crystal Oscillator mode
01 = XT Crystal Oscillator mode
00 = EC (External Clock) mode
Watchdog Timer Enable bit
1 = Watchdog Timer always enabled (LPRC Oscillator cannot be
0 = Watchdog Timer enabled/disabled by user software (LPRC can
Watchdog Timer Window Enable bit
1 = Watchdog Timer in Non-Window mode
0 = Watchdog Timer in Window mode
Preliminary
user-selected oscillator source when ready
disabled. Clearing the SWDTEN bit in the RCON register has no
effect.)
be disabled by clearing the SWDTEN bit in the RCON register)
Description
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