DSPIC33EP512MU810T-I/PT Microchip Technology, DSPIC33EP512MU810T-I/PT Datasheet - Page 118

• Manufacturer Part Number: DSPIC33EP512MU810T-I/PT
• Description: 100 PINS, 512KB Flash, 52KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 12x12x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP512MU810T-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 512KB (170K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 24K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
4.2.10
The W15 register serves as a dedicated software Stack
Pointer (SP) and is automatically modified by exception
processing, subroutine calls and returns; however,
W15 can be referenced by any instruction in the same
manner as all other W registers. This simplifies
reading, writing and manipulating of the Stack Pointer
(for example, creating stack frames).
W15 is initialized to 0x1000 during all Resets. This
address ensures that the SP points to valid RAM in all
dsPIC33EPXXXMU806/810/814
PIC24EPXXXGU810/814 devices and permits stack
availability for non-maskable trap exceptions. These
can occur before the SP is initialized by the user
software.
initialization to any location within data space.
The Stack Pointer always points to the first available
free word and fills the software stack working from
lower toward higher addresses.
how it pre-decrements for a stack pop (read) and post-
increments for a stack push (writes).
When the PC is pushed onto the stack, PC<15:0> is
pushed onto the first available stack word, then
PC<22:16> is pushed into the second available stack
location. For a PC push during any CALL instruction,
the MSB of the PC is zero-extended before the push,
as shown in
the MSB of the PC is concatenated with the lower 8 bits
of the CPU STATUS register, SR. This allows the
contents of SRL to be preserved automatically during
interrupt processing.
DS70616E-page 118
Note:
Note 1: To main system Stack Pointer (W15)
2: As the stack can be placed in and
You
SOFTWARE STACK
To protect against misaligned stack
accesses, W15<0> is fixed to ‘0’ by the
hardware.
coherency, W15 is never subject to
(EDS)
restricted to the address range of
0x0000 to 0xFFFF. The same applies to
W14 when used as a Stack Frame
Pointer (SFA = 1).
across X, Y, and DMA RAM spaces,
care must be exercised regarding its
use, particularly with regard to local
automatic variables in a C development
environment.
Figure
can
4-9. During exception processing,
paging,
reprogram
and
Figure 4-9
the
is
SP
therefore
illustrates
during
and
Preliminary
FIGURE 4-9:
4.3
The addressing modes shown in
basis of the addressing modes optimized to support the
specific features of individual instructions. The
addressing modes provided in the MAC class of
instructions differ from those in the other instruction
types.
4.3.1
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first 8192
bytes of data memory (near data space). Most file
register instructions employ a working register, W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space.
4.3.2
The three-operand MCU instructions are of the form:
Operand 3 = Operand 1 <function> Operand 2
where Operand 1 is always a working register (that is,
the addressing mode can only be Register Direct),
which is referred to as Wb. Operand 2 can be a W reg-
ister, fetched from data memory, or a 5-bit literal. The
result location can be either a W register or a data
memory location. The following addressing modes are
supported by MCU instructions:
• Register Direct
• Register Indirect
• Register Indirect Post-Modified
• Register Indirect Pre-Modified
• 5-bit or 10-bit Literal
0x0000
Note:
Instruction Addressing Modes
15
b‘000000000’
FILE REGISTER INSTRUCTIONS
MCU INSTRUCTIONS
Not all instructions support all the
addressing modes given above. Individ-
ual instructions can support different
subsets of these addressing modes.
<Free Word>
PC<15:1>
 2009-2011 Microchip Technology Inc.
CALL STACK FRAME
PC<22:16>
0
Table 4-68
W15 (before CALL)
W15 (after CALL)
CALL
SUBR
form the