DSPIC33EP512MU810T-I/PT Microchip Technology, DSPIC33EP512MU810T-I/PT Datasheet - Page 264

• Manufacturer Part Number: DSPIC33EP512MU810T-I/PT
• Description: 100 PINS, 512KB Flash, 52KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 12x12x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP512MU810T-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 512KB (170K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 24K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
REGISTER 15-2:
DS70616E-page 264
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11-9
bit 8
bit 7
bit 6
bit 5
Note 1:
OCTRIG
FLTMD
R/W-0
R/W-0
2:
Do not use the OCx module as its own synchronization or trigger source.
When the OCy module is turned OFF, it sends a trigger out signal. If the OCx module use the OCy module
as a trigger source, the OCy module must be unselected as a trigger source prior to disabling it.
FLTMD: Fault Mode Select bit
1 = Fault mode is maintained until the Fault source is removed; the corresponding OCFLTx bit is
0 = Fault mode is maintained until the Fault source is removed and a new PWM period starts
FLTOUT: Fault Out bit
1 = PWM output is driven high on a Fault
0 = PWM output is driven low on a Fault
FLTTRIEN: Fault Output State Select bit
1 = OCx pin is tri-stated on Fault condition
0 = OCx pin I/O state defined by FLTOUT bit on Fault condition
OCINV: OCMP Invert bit
1 = OCx output is inverted
0 = OCx output is not inverted
Unimplemented: Read as ‘0’
OC32: Cascade Two OCx Modules Enable bit (32-bit operation)
1 = Cascade module operation enabled
0 = Cascade module operation disabled
OCTRIG: OCx Trigger/Sync Select bit
1 = Trigger OCx from source designated by SYNCSELx bits
0 = Synchronize OCx with source designated by SYNCSELx bits
TRIGSTAT: Timer Trigger Status bit
1 = Timer source has been triggered and is running
0 = Timer source has not been triggered and is being held clear
OCTRIS: OCx Output Pin Direction Select bit
1 = OCx is tri-stated
0 = Output compare module drives the OCx pin
TRIGSTAT
R/W-0 HS
FLTOUT
R/W-0
cleared in software and a new PWM period starts
OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2
HS = Hardware Settable bit
W = Writable bit
‘1’ = Bit is set
FLTTRIEN
OCTRIS
R/W-0
R/W-0
OCINV
R/W-0
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-1
U-0
—
SYNCSEL<4:0>
R/W-1
U-0
—
 2009-2011 Microchip Technology Inc.
x = Bit is unknown
R/W-0
U-0
—
R/W-0
R/W-0
OC32
bit 8
bit 0