DSPIC33EP512MU810T-I/PT Microchip Technology, DSPIC33EP512MU810T-I/PT Datasheet - Page 126

• Manufacturer Part Number: DSPIC33EP512MU810T-I/PT
• Description: 100 PINS, 512KB Flash, 52KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 12x12x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP512MU810T-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 512KB (170K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 24K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
5.2
The
PIC24EPXXXGU810/814 Flash program memory
array is organized into rows of 128 instructions or 384
bytes. RTSP allows the user application to erase a
page of memory, which consists of eight rows (1024
instructions) at a time, and to program one row or one
word at a time.
gramming times. The 8-row erase pages and single
row write rows are edge-aligned from the beginning of
program memory, on boundaries of 3072 bytes and
384 bytes, respectively.
The program memory implements holding buffers,
which are located in the write latch area, that can
contain 128 instructions of programming data. Prior to
the actual programming operation, the write data must
be loaded into the buffers sequentially. The instruction
words loaded must always be from a group of 64
boundary.
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWT instructions
to load the buffers. Programming is performed by
setting the control bits in the NVMCON register. A total
of 128 TBLWTL and TBLWTH instructions are required
to load the instructions.
All of the table write operations are single-word writes
(two instruction cycles) because only the buffers are
written.
programming each row. For more information on eras-
ing and programming Flash memory, refer to Section
5.
“dsPIC33E/PIC24E Family Reference Manual”.
5.3
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode.
programming operation is finished.
The programming time depends on the FRC accuracy
(see
Tuning register (see
formula to calculate the minimum and maximum values
for the Row Write Time, Page Erase Time and Word
Write Cycle Time parameters (see
DS70616E-page 126
“Flash
Table
The
RTSP Operation
Programming Operations
A
dsPIC33EPXXXMU806/810/814
32-19) and the value of the FRC Oscillator
programming
Programming”
processor
Table 32-12
Register
stalls
lists typical erase and pro-
cycle
9-4). Use the following
(DS70609)
Table
(waits)
is
32-12).
required
until
in
and
Preliminary
the
the
for
EQUATION 5-1:
For example, if the device is operating at +125°C, the
FRC accuracy will be ±5%. If the TUN<5:0> bits (see
Register
write time is equal to
EQUATION 5-2:
The maximum row write time is equal to
EQUATION 5-3:
Setting the WR bit (NVMCON<15>) starts the
operation, and the WR bit is automatically cleared
when the operation is finished.
5.4
Four SFRs are used to read and write the program
Flash memory: NVMCON, NVMKEY, NVMADRU, and
NVMADR.
The NVMCON register
blocks are to be erased, which memory type is to be
programmed and the start of the programming cycle.
NVMKEY
used for write protection. To start a programming or
erase
consecutively write 0x55 and 0xAA to the NVMKEY
register.
There are two NVM address registers: NVMADRU and
NVMADR. These two registers, when concatenated,
form the 24-bit effective address (EA) of the selected
row or word for programming operations, or the
selected page for erase operations.
The NVMADRU register is used to hold the upper 8 bits
of the EA, while the NVMADR register is used to hold
the lower 16 bits of the EA.
T
T
RW
RW
------------------------------------------------------------------------------------------------------------------------- -
7.37 MHz
=
=
--------------------------------------------------------------------------------------------- - 1.586ms
7.37 MHz
---------------------------------------------------------------------------------------------- 1.435ms
7.37 MHz
sequence,
9-4) are set to ‘b111111, the minimum row
Control Registers
(Register


FRC Accuracy


 2009-2011 Microchip Technology Inc.


11064 Cycles
11064 Cycles
1 0.05
5-4) is a write-only register that is
1
Equation
–
+
the
PROGRAMMING TIME
MINIMUM ROW WRITE
TIME
MAXIMUM ROW WRITE
TIME
0.05
(Register
T


user


%
5-2.


1 0.00375
1 0.00375

–
–
5-1) controls which

application
FRC Tuning
Equation


=
=
%
must
5-3.