DSPIC33EP512MU810T-I/PT Microchip Technology, DSPIC33EP512MU810T-I/PT Datasheet - Page 562

• Manufacturer Part Number: DSPIC33EP512MU810T-I/PT
• Description: 100 PINS, 512KB Flash, 52KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 12x12x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP512MU810T-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 512KB (170K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 24K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
ECAN Registers
ECAN Transmit/Receive Error Count Register (CiEC) ..... 338
ECAN TX/RX Buffer m Control Register (CiTRmnCON) .. 349
Electrical Characteristics................................................... 459
Enhanced CAN Module..................................................... 329
Equations
Errata .................................................................................. 20
F
Flash Program Memory..................................................... 125
Flexible Configuration ....................................................... 437
H
High-Speed PWM ............................................................. 267
DS70616E-page 562
CiFIFO register ......................................................... 335
CiFMSKSEL1 register ............................................... 344
CiFMSKSEL2 register ............................................... 345
CiINTE register ......................................................... 337
CiINTF register.......................................................... 336
CiRXFnEID register .................................................. 344
CiRXFnSID register .................................................. 343
CiRXFUL1 register .................................................... 347
CiRXFUL2 register .................................................... 347
CiRXMnEID register.................................................. 346
CiRXMnSID register.................................................. 346
CiRXOVF1 register ................................................... 348
CiRXOVF2 register ................................................... 348
CiTRmnCON register ................................................ 349
CiVEC register .......................................................... 333
Modes of Operation .................................................. 330
Overview ................................................................... 329
Acceptance Filter Enable Register (CiFEN1)............ 340
Acceptance Filter Extended Identifier Register n
Acceptance Filter Mask Extended Identifier Register n
Acceptance Filter Mask Standard Identifier Register n
Acceptance Filter Standard Identifier Register n
Baud Rate Configuration Register 1 (CiCFG1) ......... 338
Baud Rate Configuration Register 2 (CiCFG2) ......... 339
Control Register 1 (CiCTRL1) ................................... 331
Control Register 2 (CiCTRL2) ................................... 332
FIFO Control Register (CiFCTRL) ............................ 334
FIFO Status Register (CiFIFO) ................................. 335
Filter 0-3 Buffer Pointer Register (CiBUFPNT1) ....... 340
Filter 12-15 Buffer Pointer Register (CiBUFPNT4) ... 342
Filter 15-8 Mask Selection Register (CiFMSKSEL2). 345
Filter 4-7 Buffer Pointer Register (CiBUFPNT2) ....... 341
Filter 7-0 Mask Selection Register (CiFMSKSEL1)... 344
Filter 8-11 Buffer Pointer Register (CiBUFPNT3) ..... 341
Interrupt Code Register (CiVEC) .............................. 333
Interrupt Enable Register (CiINTE) ........................... 337
Interrupt Flag Register (CiINTF) ............................... 336
Receive Buffer Full Register 1 (CiRXFUL1).............. 347
Receive Buffer Full Register 2 (CiRXFUL2).............. 347
Receive Buffer Overflow Register 2 (CiRXOVF2)..... 348
Receive Overflow Register (CiRXOVF1) .................. 348
AC ............................................................................. 471
Device Operating Frequency .................................... 164
Control Registers ...................................................... 126
Operations ................................................................ 126
Programming Algorithm ............................................ 128
RTSP Operation........................................................ 126
Table Instructions...................................................... 125
(CiRXFnEID) ..................................................... 344
(CiRXMnEID) .................................................... 346
(CiRXMnSID) .................................................... 346
(CiRXFnSID) ..................................................... 343
Preliminary
I
I/O Ports............................................................................ 189
In-Circuit Debugger........................................................... 443
In-Circuit Emulation .......................................................... 437
In-Circuit Serial Programming (ICSP)....................... 437, 443
Input Capture .................................................................... 257
Input Change Notification ................................................. 190
Instruction Addressing Modes .......................................... 118
Instruction Set
Instruction-Based Power-Saving Modes........................... 175
Internal RC Oscillator
Internet Address ............................................................... 567
Interrupt Control and Status Registers ............................. 138
Interrupt Vector Table (IVT) .............................................. 133
Interrupts Coincident with Power Save Instructions ......... 176
J
JTAG Boundary Scan Interface ........................................ 437
JTAG Interface.................................................................. 443
M
Memory Organization ......................................................... 43
Microchip Internet Web Site.............................................. 567
Modulo Addressing ........................................................... 120
Most Recent DMA DPSRAM Address Low Register ........ 155
Most Recent DMA DPSRAM High Address...................... 155
MPLAB ASM30 Assembler, Linker, Librarian ................... 456
MPLAB Integrated Development Environment Software.. 455
MPLAB PM3 Device Programmer .................................... 458
MPLAB REAL ICE In-Circuit Emulator System ................ 457
MPLINK Object Linker/MPLIB Object Librarian ................ 456
O
Open-Drain Configuration................................................. 190
Output Compare ............................................................... 261
P
Packaging ......................................................................... 531
Peripheral Module Disable (PMD) .................................... 176
Peripherals supported by DMA......................................... 147
Pinout I/O Descriptions (table)............................................ 23
Power-Saving Features .................................................... 175
Parallel I/O (PIO) ...................................................... 189
Write/Read Timing .................................................... 190
Registers .................................................................. 258
File Register Instructions .......................................... 118
Fundamental Modes Supported ............................... 119
MAC Instructions ...................................................... 119
MCU Instructions ...................................................... 118
Move and Accumulator Instructions.......................... 119
Other Instructions ..................................................... 119
Overview................................................................... 448
Summary .................................................................. 445
Idle ............................................................................ 176
Sleep ........................................................................ 175
Use with WDT........................................................... 442
IFSx .......................................................................... 138
INTCON1 .................................................................. 138
INTCON2 .................................................................. 138
Applicability............................................................... 121
Operation Example ................................................... 120
Start and End Address ............................................. 120
W Address Register Selection .................................. 120
Details....................................................................... 536
Marking ............................................................. 531, 532
 2009-2011 Microchip Technology Inc.