EP20K400CF672C8 Altera, EP20K400CF672C8 Datasheet - Page 32

• Manufacturer Part Number: EP20K400CF672C8
• Description: APEX 20KC
• Manufacturer: Altera

APEX 20KC Programmable Logic Device Data Sheet
Figure 21. ESB in Input/Output Clock Mode
Note to
(1)
32
wraddress[ ]
rdaddress[ ]
outclock
outclken
inclken
inclock
data[ ]
Dedicated Clocks
wren
rden
All registers can be cleared asynchronously by ESB local interconnect signals, global signals, or the chip-wide reset.
Figure
4
Dedicated Inputs &
Global Signals
21:
4
Input/Output Clock Mode
The input/output clock mode contains two clocks. One clock controls all
registers for inputs into the ESB: data input, WE, RE, read address, and
write address. The other clock controls the ESB data output registers. The
ESB also supports clock enable and asynchronous clear signals; these
signals also control the reading and writing of registers independently.
Input/output clock mode is commonly used for applications where the
reads and writes occur at the same system frequency, but require different
clock enable signals for the input and output registers.
the ESB in input/output clock mode.
D
ENA
D
ENA
D
ENA
Q
Q
Q
Note (1)
Generator
D
ENA
Pulse
Write
D
ENA
Q
Q
Data In
Read Address
Write Address
Read Enable
Write Enable
RAM/ROM
1,024 × 2
2,048 × 1
Data Out
128 × 16
256 × 8
512 × 4
D
ENA
Figure 21
Q
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