CP3BT10G38 National Semiconductor, CP3BT10G38 Datasheet - Page 130

• Manufacturer Part Number: CP3BT10G38
• Description: IC CPU RISC W/LLC&USB 100-LQFP
• Manufacturer: National Semiconductor

Specifications of CP3BT10G38

• Applications: Connectivity Processor
• Core Processor: CR16C
• Program Memory Type: FLASH (256 kB)
• Controller Series: CP3000
• Ram Size: 10K x 8
• Interface: Bluetooth, ACCESS.bus, Audio, UART, USB, Microwire/SPI
• Number Of I /o: 37
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *CP3BT10G38

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21.0 ACCESS.bus Interface
The ACCESS.bus interface module (ACB) is a two-wire se-
rial interface compatible with the ACCESS.bus physical lay-
er. It permits easy interfacing to a wide range of low-cost
memories and I/O devices, including: EEPROMs, SRAMs,
timers, A/D converters, D/A converters, clock chips, and pe-
ripheral drivers. It is compatible with Intel’s SMBus and Phil-
ips’ I
or slave, and can maintain bidirectional communications
with both multiple master and slave devices.
This section presents an overview of the bus protocol, and
its implementation by the module.
21.1
The ACCESS.bus protocol uses a two-wire interface for bi-
directional communication between the devices connected
to the bus. The two interface signals are the Serial Data Line
(SDA) and the Serial Clock Line (SCL). These signals
should be connected to the positive supply, through pull-up
resistors, to keep the signals high when the bus is idle.
The ACCESS.bus protocol supports multiple master and
slave transmitters and receivers. Each bus device has a
unique address and can operate as a transmitter or a re-
ceiver (though some peripherals are only receivers).
During data transactions, the master device initiates the
transaction, generates the clock signal, and terminates the
transaction. For example, when the ACB initiates a data
transaction with an ACCESS.bus peripheral, the ACB be-
comes the master. When the peripheral responds and
transmits data to the ACB, their master/slave (data transac-
tion initiator and clock generator) relationship is unchanged,
even though their transmitter/receiver functions are re-
versed.
21.1.1
One data bit is transferred during each clock period. Data is
sampled during the high phase of the serial clock (SCL).
Consequently, throughout the clock high phase, the data
must remain stable (see Figure 55). Any change on the SDA
signal during the high phase of the SCL clock and in the
middle of a transaction aborts the current transaction. New
data must be driven during the low phase of the SCL clock.
This protocol permits a single data line to transfer both com-
ACCESS.bus master and slave
Supports polling and interrupt-controlled operation
Generate a wake-up signal on detection of a Start Con-
dition, while in power-down mode
Optional internal pull-up on SDA and SCL pins
2
C bus. The module can be configured as a bus master
ACB PROTOCOL OVERVIEW
Data Transactions
130
mand/control information and data using the synchronous
serial clock.
Each data transaction is composed of a Start Condition, a
number of byte transfers (programmed by software), and a
Stop Condition to terminate the transaction. Each byte is
transferred with the most significant bit first, and after each
byte, an Acknowledge signal must follow.
At each clock cycle, the slave can stall the master while it
handles the previous data, or prepares new data. This can
be performed for each bit transferred or on a byte boundary
by the slave holding SCL low to extend the clock-low period.
Typically, slaves extend the first clock cycle of a transfer if a
byte read has not yet been stored, or if the next byte to be
transmitted is not yet ready. Some microcontrollers with lim-
ited hardware support for ACCESS.bus extend the access
after each bit, to allow software time to handle this bit.
Start and Stop
The ACCESS.bus master generates Start and Stop Condi-
tions (control codes). After a Start Condition is generated,
the bus is considered busy and it retains this status until a
certain time after a Stop Condition is generated. A high-to-
low transition of the data line (SDA) while the clock (SCL) is
high indicates a Start Condition. A low-to-high transition of
the SDA line while the SCL is high indicates a Stop Condi-
tion (Figure 56).
In addition to the first Start Condition, a repeated Start Con-
dition can be generated in the middle of a transaction. This
allows another device to be accessed, or a change in the di-
rection of the data transfer.
SDA
SCL
SDA
SCL
Start
Condition
Figure 56. Start and Stop Conditions
S
Data Line
Stable:
Data Valid
Figure 55. Bit Transfer
Change
of Data
Allowed
Stop
Condition
P
DS075
DS076