CP3BT10G38 National Semiconductor, CP3BT10G38 Datasheet - Page 78

• Manufacturer Part Number: CP3BT10G38
• Description: IC CPU RISC W/LLC&USB 100-LQFP
• Manufacturer: National Semiconductor

Specifications of CP3BT10G38

• Applications: Connectivity Processor
• Core Processor: CR16C
• Program Memory Type: FLASH (256 kB)
• Controller Series: CP3000
• Ram Size: 10K x 8
• Interface: Bluetooth, ACCESS.bus, Audio, UART, USB, Microwire/SPI
• Number Of I /o: 37
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *CP3BT10G38

www.national.com
Receive Endpoint FIFO Operation (RXFIFO1, RXFIFO2,
The Receive FIFOs for endpoints 2, 4, and 6 support bulk,
interrupt, and isochronous USB packet transfers larger than
the actual FIFO size. If the packet length exceeds the FIFO
size, software must read the FIFO contents while the USB
packet is being received on the bus. Figure 28 shows the
detailed behavior of receive FIFOs.
RFnS
RXRP
RXWP
RXFL
RCOUNT
RXFL = RXRP
FLUSH (Resets RXRP and RXWP)
RXFIFO3)
Figure 28. Receive FIFO Operation
RFnS
The Receive FIFO n Size is the total number
of bytes available within the FIFO.
The Receive Read Pointer is incremented
with every read by software from the receive
FIFO. This pointer wraps around to zero if
RFnS is reached. RXRP is never incremented
beyond the value of RXWP. If an attempt is
made to read more bytes than are actually
available (FIFO underrun), the last byte is
read repeatedly.
The Receive Write Pointer is incremented ev-
ery time the Endpoint Controller writes to the
receive FIFO. This pointer wraps around to
zero if RFnS is reached. An overrun condition
occurs if RXRP equals RXWP and an attempt
is made to write an additional byte.
The Receive FIFO Level indicates how many
more bytes can be received until an overrun
condition occurs with the next write to the
FIFO. A FIFO warning is issued if RXFL de-
creases to a specific value. The respective
WARNn bit in the FWR register is set if RXFL
is equal to or less than the number specified
by the RFWL bit in the RXCn register.
The Receive FIFO Count indicates how many
bytes can be read from the receive FIFO. This
value is accessible by software from the RXSn
register.
-
RXWP (= RFnS
RX FIFO n
-
1
0X0
+
-
RCOUNT)
RXRP
+
+
RCOUNT = RXWP
RXWP
-
DS052
RXRF
78
16.3
The USB node has a set of memory-mapped registers that
can be read/written from the CPU bus to control the USB in-
terface. Some register bits are reserved; reading from these
bits returns undefined data. Reserved register bits must al-
ways be written with 0.
DMACNTRL
DMAMSK
DMAERR
MCNTRL
NAKMSK
DMACNT
ALTMSK
MAMSK
FWMSK
RXMSK
DMAEV
TXMSK
NAKEV
ALTEV
FWEV
Name
NFSR
MAEV
RXEV
TXEV
FNH
FNL
FAR
MIR
USB CONTROLLER REGISTERS
Table 37 USB Controller Registers
FF FD8Ch
FF FD9Ch
FF FDAAh
FF FDACh
FF FDAEh
FF FD80h
FF FD8Ah
FF FD90h
FF FD8Eh
FF FD92h
FF FD94h
FF FD96h
FF FD98h
FF FD9Ah
FF FD9Eh
FF FDA0h
FF FDA2h
FF FDA4h
FF FDA6h
FF FD88h
FF FDA8h
FF FDB0h
FF FDB2h
Address
Node Functional State
Main Control Register
DMA Control Register
DMA Count Register
Main Event Register
FIFO Warning Event
Frame Number High
DMA Event Register
NAK Event Register
FIFO Warning Mask
DMA Mask Register
Main Mask Register
Frame Number Low
NAK Mask Register
DMA Error Register
Function Address
Alternate Event
Alternate Mask
Transmit Event
Mirror Register
Transmit Mask
Receive Event
Receive Mask
Byte Register
Byte Register
Description
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register