CP3BT10G38 National Semiconductor, CP3BT10G38 Datasheet - Page 45

• Manufacturer Part Number: CP3BT10G38
• Description: IC CPU RISC W/LLC&USB 100-LQFP
• Manufacturer: National Semiconductor

Specifications of CP3BT10G38

• Applications: Connectivity Processor
• Core Processor: CR16C
• Program Memory Type: FLASH (256 kB)
• Controller Series: CP3000
• Ram Size: 10K x 8
• Interface: Bluetooth, ACCESS.bus, Audio, UART, USB, Microwire/SPI
• Number Of I /o: 37
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *CP3BT10G38

9.6.6
The Block Length register is a 16-bit, read/write register. It
holds the number of DMA transfers to be performed for the
next block. Writing this register automatically sets the DM-
ASTAT.VLD bit.
Note: 0000h is interpreted as 2
9.6.7
The DMA Control register n is a word-wide, read/write reg-
ister that controls the operation of DMA channel n. This reg-
ister is cleared at reset. Reserved bits must be written with
0.
CHEN
ETC
EOVR
TCS
IND
BPC
Res.
15
15
7
DMA Control Register (DMACNTLn)
Block Length Register (BLTRn)
OT
14
6
INCB
The Channel Enable bit must be set to enable
any DMA operation on this channel. Writing a
1 to this bit starts a new DMA transfer even if
it is currently a 1. If all DMACNTLn.CHEN bits
are clear, the DMA clock is disabled to reduce
power.
0
1
If the Enable Interrupt on Terminal Count bit is
set, it enables an interrupt when the DMAS-
TAT.TC bit is set.
0
1
If the Enable Interrupt on OVR bit is set, it en-
ables an interrupt when the DMASTAT.OVR
bit is set.
0
1
The Transfer Cycle Size bit specifies the num-
ber of bytes transferred in each DMA transfer
cycle. In direct (fly-by) mode, undefined re-
sults occur if the TCS bit is not equal to the ad-
dressed memory bus width.
0
1
The Direct/Indirect Transfer bit specifies the
transfer type.
0
1
–
–
–
–
–
–
–
–
–
–
DIR
13
Channel disabled.
Channel enabled.
Interrupt disabled.
Interrupt enabled.
Interrupt disabled.
Interrupt enabled.
Byte transfers (8 bits per cycle).
Word transfers (16 bits per cycle).
Direct transfer (flyby).
Indirect transfer (memory-to-memory).
5
Block Length
ADB
IND
12
4
TCS EOVR ETC CHEN
11
16
3
INCA
-1 transfer cycles.
10
2
ADA SWRQ
9
1
8
0
0
45
DIR
OT
BPC
SWRQ
ADA
INCA
ADB
INCB
The Transfer Direction bit specifies the direc-
tion of the transfer relative to Device A.
0
1
The Operation Type bit specifies the operation
mode of the DMA controller.
0
1
The Bus Policy Control bit specifies the bus
policy applied by the DMA controller. The op-
eration mode can be either intermittent (cycle
stealing) or continuous (burst).
0
1
The Software DMA Request bit is written with
a 1 to initiate a software DMA request. Writing
a 0 to this bit deactivates the software DMA
request. The SWRQ bit must only be written
when the DMRQ signal for this channel is in-
active (DMASTAT.CHAC = 0).
0
1
If the Device A Address Control bit is set, it en-
ables updating the Device A address.
0 – ADCAn address unchanged.
1 – ADCAn address incremented or decre-
The Increment/Decrement ADCAn field spec-
ifies the step size for the Device A address in-
crement/decrement.
00 – Increment ADCAn register by 1.
01 – Increment ADCAn register by 2.
10 – Decrement ADCAn register by 1.
11 – Decrement ADCAn register by 2.
If the Device B Address Control bit is set, it en-
ables updating the Device B Address.
0
1
The Increment/Decrement ADCBn field spec-
ifies the step size for the Device B address in-
crement/decrement.
00 – Increment ADCBn register by 1.
01 – Increment ADCBn register by 2.
10 – Decrement ADCBn register by 1.
11 – Decrement ADCBn register by 2.
–
–
–
–
–
–
–
–
–
–
Device A (pointed to by the ADCAn regis-
ter) is the source. In Fly-By mode a read
transaction is initialized.
Device A (pointed to by the ADCAn regis-
ter) is the destination. In Fly-By mode a
write transaction is initialized.
Single-buffer mode or double-buffer mode
enabled.
Auto-Initialize mode enabled.
Intermittent operation. The DMAC chan-
nel relinquishes the bus after each trans-
action, even if the request is still asserted.
Continuous operation. The DMAC chan-
nel n uses the bus continuously as long
as the request is asserted. This mode can
only be used for software DMA requests.
For hardware DMA requests, the BPC bit
must be clear.
Software DMA request is inactive.
Software DMA request is active.
mented, according to INCA field of
DMACNTLn register.
ADCBn address unchanged.
ADCBn address incremented or decre-
mented, according to INCB field of
DMACNTLn register.
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