PCK2001MDB NXP Semiconductors, PCK2001MDB Datasheet - Page 7

Clock Buffer PII CLCK DRVR MOBILE

PCK2001MDB

Manufacturer Part Number
PCK2001MDB
Description
Clock Buffer PII CLCK DRVR MOBILE
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PCK2001MDB

Mounting Style
SMD/SMT
Package / Case
SOT-341
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PCK2001MDB,112

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PCK2001MDB
Manufacturer:
PHILIPS
Quantity:
40
Part Number:
PCK2001MDB
Manufacturer:
NXP/恩智浦
Quantity:
20 000
1. Clock period and skew are measured on the rising edge at 1.5 V.
2. T
3. T
4. T
5. Duty cycle should be tested with a 50/50% input.
6. Over MIN (20 pF) to MAX (30 pF) discrete load, process, voltage, and temperature.
7. Input edge rate for these tests must be faster than 1 V/ns.
8. Calculated at minimum edge rate (1.5 ns) to guarantee 45/55% duty cycle at 1.5 V. Pulsewidth is required to be wider at the faster edge to
9. All typical values are at V
10. Typical is measured with MAX (30 pf) discrete load.
11. Typical is measured with MIN (20 pf) discrete load.
Philips Semiconductors
AC CHARACTERISTICS
NOTES:
2000 May 17
DUTY CYCLE
14.318–150 MHz I
T
T
ensure duty cycle specification is met.
SYMBOL
T
T
PZL
PLZ
T
T
SDKH
SDKL
SDRISE
T
T
T
T
T
T
T
T
T
SDRISE
SDFALL
SDSKW
DDSKW
T
T
SDKH
SDKH
SDKH
SDKP
SDKL
SDKP
SDKL
SDKP
SDKL
PLH
PHL
, T
, T
is measured at 0.4 V as shown in Figure 3.
PZH
PHZ
is measured at 2.4 V as shown in Figure 3.
and T
SDFALL
SDRAM buffer LH propagation delay
SDRAM buffer HL propagation delay
SDRAM buffer disable time
SDRAM buffer enable time
SDRAM CLK HIGH time
SDRAM CLK HIGH time
SDRAM CLK HIGH time
are measured as a transition through the threshold region V
SDRAM CLK LOW time
SDRAM CLK LOW time
SDRAM CLK LOW time
SDRAM Bus CLK skew
Device to device skew
SDRAM CLK period
SDRAM CLK period
SDRAM CLK period
CC
Output Duty Cycle
SDRAM rise time
SDRAM fall time
PARAMETER
= 3.3 V and T
2
C 1:10 clock buffer
amb
= 25 C.
Measured at 1.5 V
TEST CONDITIONS
100 MHz
133 MHz
66 MHz
7
NOTES
4, 6, 10
4, 6, 11
2, 6, 8
3, 6, 8
2, 6, 8
3, 6, 8
2, 6, 8
3, 6, 8
5, 6, 7
1, 6
1, 6
1, 6
1, 6
6, 7
6, 7
6, 7
6, 7
OL
= 0.4 V and V
MIN
15.0
10.0
5.6
5.3
3.3
3.1
7.4
2.6
2.1
1.5
1.5
1.0
1.0
1.0
1.0
45
T
amb
OH
= 2.4 V (1 mA) JEDEC specification.
= 0 C to +70 C
LIMITS
TYP
10.01
15.2
150
7.8
7.4
5.1
4.9
7.5
3.2
2.8
2.0
2.9
2.5
2.5
2.6
2.7
52
9
PCK2001M
MAX
15.5
10.5
250
250
Product specification
8.4
8.0
5.7
5.5
7.7
3.8
3.5
4.0
4.0
3.5
3.5
5.0
5.0
55
UNIT
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
%

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