PHB21N06LT,118 NXP Semiconductors, PHB21N06LT,118 Datasheet

PHB21N06LT,118

Manufacturer Part Number

PHB21N06LT,118

Description

MOSFET N-CH 55V 19A SOT404

Manufacturer

NXP Semiconductors

Series

TrenchMOS™r

Datasheet

1.PHB21N06LT118.pdf (11 pages)

Specifications of PHB21N06LT,118

Package / Case

D²Pak, TO-263 (2 leads + tab)

Mounting Type

Surface Mount

Power - Max

56W

Fet Type

MOSFET N-Channel, Metal Oxide

Gate Charge (qg) @ Vgs

9.4nC @ 5V

Vgs(th) (max) @ Id

2V @ 1mA

Current - Continuous Drain (id) @ 25° C

19A

Drain To Source Voltage (vdss)

55V

Fet Feature

Logic Level Gate

Rds On (max) @ Id, Vgs

70 mOhm @ 10A, 10V

Minimum Operating Temperature

- 55 C

Configuration

Single

Transistor Polarity

N-Channel

Resistance Drain-source Rds (on)

0.07 Ohm @ 10 V

Drain-source Breakdown Voltage

55 V

Gate-source Breakdown Voltage

+/- 15 V

Continuous Drain Current

19 A

Power Dissipation

56000 mW

Maximum Operating Temperature

+ 175 C

Mounting Style

SMD/SMT

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant, Lead free / RoHS Compliant

Other names

934054570118::PHB21N06LT /T3::PHB21N06LT /T3

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Philips Semiconductors

FEATURES

• ’Trench’ technology

• Low on-state resistance

• Fast switching

• Logic level compatible

GENERAL DESCRIPTION

N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’trench’ technology.

Applications:-

• d.c. to d.c. converters

• switched mode power supplies

The PHP21N06LT is supplied in the SOT78 (TO220AB) conventional leaded package.

The PHB21N06LT is supplied in the SOT404 (D

The PHD21N06LT is supplied in the SOT428 (DPAK) surface mounting package.

PINNING

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

1 It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages.

August 1999

N-channel TrenchMOS

Logic level FET

SYMBOL PARAMETER

DSS

DGR

GSM

, T

tab

stg

gate

drain

source

drain

DESCRIPTION

Drain-source voltage

Drain-gate voltage

Gate-source voltage

Pulsed gate-source voltage

Continuous drain current

Pulsed drain current

Total power dissipation

Operating junction and

storage temperature

SOT78 (TO220AB)

transistor

SYMBOL

tab

CONDITIONS

1 2 3

= 25 ˚C to 175˚C

= 25 ˚C to 175˚C; R

= 25 ˚C

= 100 ˚C

= 25 ˚C

150˚C

PAK) surface mounting package.

SOT404 (D

= 20 k

tab

PHP21N06LT, PHB21N06LT

PAK)

QUICK REFERENCE DATA

DS(ON)

MIN.

- 55

SOT428 (DPAK)

70 m (V

75 m (V

DSS

Product specification

= 19 A

PHD21N06LT

= 55 V

MAX.

175

tab

= 10 V)

Rev 1.500

= 5 V)

UNIT

˚C

Related parts for PHB21N06LT,118

PHB21N06LT,118 Summary of contents

Page 1

Philips Semiconductors N-channel TrenchMOS Logic level FET FEATURES • ’Trench’ technology • Low on-state resistance • Fast switching • Logic level compatible GENERAL DESCRIPTION N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’trench’ technology. Applications:- ...

Page 2

Philips Semiconductors N-channel TrenchMOS Logic level FET AVALANCHE ENERGY LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER E Non-repetitive avalanche AS energy I Peak non-repetitive AS avalanche current THERMAL RESISTANCES SYMBOL PARAMETER R ...

Page 3

Philips Semiconductors N-channel TrenchMOS Logic level FET REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS T = 25˚C unless otherwise specified j SYMBOL PARAMETER I Continuous source current S (body diode) I Pulsed source current (body SM diode) V Diode forward voltage ...

Page 4

Philips Semiconductors N-channel TrenchMOS Logic level FET Drain Current VGS = 10V 0.2 0.4 0.6 0.8 1 1.2 Drain-Source Voltage, VDS (V) Fig.5. Typical output ...

Page 5

Philips Semiconductors N-channel TrenchMOS Logic level FET Drain current, ID (A) 1.0E-01 1.0E-02 1.0E-03 minimum typical 1.0E-04 1.0E-05 1.0E-06 0 0.5 1 1.5 Gate-source voltage, VGS (V) Fig.11. Sub-threshold drain current f(V ; conditions ˚C; ...

Page 6

Philips Semiconductors N-channel TrenchMOS Logic level FET MECHANICAL DATA Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220 DIMENSIONS (mm are the original dimensions UNIT A 1 4.5 1.39 0.9 mm 4.1 1.27 0.7 Note 1. Terminals ...

Page 7

Philips Semiconductors N-channel TrenchMOS Logic level FET MECHANICAL DATA Plastic single-ended surface mounted package (Philips version of D (one lead cropped DIMENSIONS (mm are the original dimensions) UNIT 4.50 1.40 mm 4.10 ...

Page 8

Philips Semiconductors N-channel TrenchMOS Logic level FET MOUNTING INSTRUCTIONS Dimensions in mm August 1999 transistor 11.5 9.0 2.0 3.8 5.08 Fig.18. SOT404 : soldering pattern for surface mounting . 8 Product specification PHP21N06LT, PHB21N06LT PHD21N06LT 17.5 Rev 1.500 ...

Page 9

Philips Semiconductors N-channel TrenchMOS Logic level FET MECHANICAL DATA Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads (one lead cropped DIMENSIONS (mm are the original dimensions ...

Page 10

Philips Semiconductors N-channel TrenchMOS Logic level FET Dimensions in mm August 1999 transistor 7.0 2.15 2.5 4.57 Fig.20. SOT428 : soldering pattern for surface mounting . 10 Product specification PHP21N06LT, PHB21N06LT PHD21N06LT 7.0 1.5 Rev 1.500 ...

Page 11

Philips Semiconductors N-channel TrenchMOS Logic level FET DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification ...

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