72V285L15TFI Integrated Device Technology (Idt), 72V285L15TFI Datasheet - Page 20

• Manufacturer Part Number: 72V285L15TFI
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 64K x 18 64-Pin STQFP Tray
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72V285L15TFI

• Package: 64STQFP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 1.125 Mb
• Organization: 64Kx18
• Data Bus Width: 18 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 3.3 V
• Operating Temperature: -40 to 85 °C

NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.
3. OE = LOW
4. W
5. OR goes LOW at 60ns + 2 RCLK cycles + t
NOTE:
1. X = 14 for the IDT72V275 and X = 15 for the IDT72V285.
Q
WCLK
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO
32,768 x 18 and 65,536 x 18
WCLK
RCLK
0
D = 32,769 for the IDT72V275 and 65,537 for the IDT72V285.
SEN
WEN
REN
- Q
PAE
PAF
1
LD
OR
, W
SI
RT
HF
n
2
, W
t
3
ENS
= first, second and third words written to the FIFO after Master Reset.
W
x
Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
ENH
BIT 0
t
t
LDS
t
ENS
DS
t
ENS
t
RTS
t
RTS
REF
t
t
ENH
LDH
.
EMPTY OFFSET
t
t
REF
t
ENH
HF
t
SKEW2
1
Figure 12. Retransmit Timing (FWFT Mode)
TM
2
t
PAF
1
W
x+1
BIT X
20
(1)
BIT 0
2
t
PAE
FULL OFFSET
3
t
A
COMMERCIAL AND INDUSTRIAL
t
t
ENH
REF
(5)
W
1
TEMPERATURE RANGES
(4)
BIT X
t
t
t
LDH
LDH
t
ENH
DH
(1)
W
4
2
t
A
4512 drw 16
t
ENH
4512 drw 15
W
3