72V285L15TFI Integrated Device Technology (Idt), 72V285L15TFI Datasheet - Page 4

• Manufacturer Part Number: 72V285L15TFI
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 64K x 18 64-Pin STQFP Tray
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72V285L15TFI

• Package: 64STQFP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 1.125 Mb
• Organization: 64Kx18
• Data Bus Width: 18 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 3.3 V
• Operating Temperature: -40 to 85 °C

PIN DESCRIPTION
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO
32,768 x 18 and 65,536 x 18
Symbol
D
MRS
PRS
RT
FWFT/SI
WCLK
WEN
RCLK
REN
OE
SEN
LD
DC
FF/IR
EF/OR
PAF
PAE
Q
V
GND
HF
0
CC
0
–D
–Q
17
17
Data Inputs
Master Reset
Partial Reset
Retransmit
First Word Fall
Through/Serial In
Write Clock
Write Enable
Read Clock
Read Enable
Output Enable
Serial Enable
Load
Don't Care
Full Flag/
Input Ready
Empty Flag/
Output Ready
Programmable
Almost-Full Flag
Programmable
Almost-Empty Flag
Half-Full Flag
Data Outputs
Power
Ground
Name
I/O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
Data inputs for a 18-bit bus.
MRS initializes the read and write pointers to zero and sets the output register to
all zeroes. During Master Reset, the FIFO is configured for either FWFT or IDT
Standard mode, one of two programmable flag default settings, and serial or
parallel programming of the offset settings.
PRS initializes the read and write pointers to zero and sets the output register to
all zeroes. During Partial Reset, the existing mode (IDT or FWFT), programming
method (serial or parallel), and programmable flag settings are all retained.
RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets
the EF flag to LOW (OR to HIGH in FWFT mode) temporarily and does not disturb
the write pointer, programming method, existing timing mode or programmable flag
settings. RT is useful to reread data from the first physical location of the FIFO.
During Master Reset, selects First Word Fall Through or IDT Standard mode.
After Master Reset, this pin functions as a serial input for loading offset registers
When enabled by WEN, the rising edge of WCLK writes data into the FIFO and
offsets into the programmable registers for parallel programming, and when
enabled by SEN, the rising edge of WCLK writes one bit of data into the
programmable register for serial programming.
WEN enables WCLK for writing data into the FIFO memory and offset registers.
When enabled by REN, the rising edge of RCLK reads data from the FIFO
memory and offsets from the programmable registers.
REN enables RCLK for reading data from the FIFO memory and offset registers.
SEN enables serial loading of programmable flag offsets.
During Master Reset, LD selects one of two partial flag default offsets (127 or 1,023
and determines the flag offset programming method, serial or parallel. After
Master Reset, this pin enables writing to and reading from the offset registers
This pin must be tied to either V
Reset.
In the IDT Standard mode, the FF function is selected. FF indicates whether or
not the FIFO memory is full. In the FWFT mode, the IR function is selected. IR
indicates whether or not there is space available for writing to the FIFO memory.
In the IDT Standard mode, the EF function is selected. EF indicates whether or
not the FIFO memory is empty. In FWFT mode, the OR function is selected.
OR indicates whether or not there is valid data available at the outputs.
PAF goes LOW if the number of words in the FIFO memory is more than
total word capacity of the FIFO minus the full offset value m, which is stored in the
Full Offset register. There are two possible default values for m: 127 or 1,023.
PAE goes LOW if the number of words in the FIFO memory is less than offset n,
which is stored in the Empty Offset register. There are two possible default values
for n: 127 or 1,023. Other values for n can be programmed into the device.
HF indicates whether the FIFO memory is more or less than half-full.
Data outputs for an 18-bit bus.
+3.3 Volt power supply pins.
Ground pins.
OE controls the output impedance of Q
TM
4
CC
Description
or GND and must not toggle after Master
n.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES