72V285L15TFI Integrated Device Technology (Idt), 72V285L15TFI Datasheet - Page 3

• Manufacturer Part Number: 72V285L15TFI
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 64K x 18 64-Pin STQFP Tray
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72V285L15TFI

• Package: 64STQFP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 1.125 Mb
• Organization: 64Kx18
• Data Bus Width: 18 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 3.3 V
• Operating Temperature: -40 to 85 °C

DESCRIPTION (Continued)
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF and
FF functions are selected in IDT Standard mode. The IR and OR functions
are selected in FWFT mode. HF, PAE and PAF are always available for
use, irrespective of timing mode.
in memory. (See Table 1 and Table 2.) Programmable offsets determine the
flag switching threshold and can be loaded by two methods: parallel or serial.
Two default offset settings are also provided, so that PAE can be set to switch
at 127 or 1,023 locations from the empty boundary and the PAF threshold can
be set at 127 or 1,023 locations from the full boundary. These choices are made
with the LD pin during Master Reset.
WCLK, are used to load the offset registers via the Serial Input (SI). For parallel
programming, WEN together with LD on each rising edge of WCLK, are used
to load the offset registers via D
of RCLK can be used to read the offsets in parallel from Q
serial or parallel offset loading has been selected.
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO
32,768 x 18 and 65,536 x 18
FIRST WORD FALL THROUGH/SERIAL INPUT
PAE and PAF can be programmed independently to switch at any point
For serial programming, SEN together with LD on each rising edge of
These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready),
PROGRAMMABLE ALMOST-FULL (PAF)
FULL FLAG/INPUT READY (FF/IR)
n
. REN together with LD on each rising edge
Figure 1. Block Diagram of Single 32,768 x 18 and 65,536 x 18 Synchronous FIFO
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
SERIAL ENABLE(SEN)
DATA IN (D
PARTIAL RESET (PRS)
LOAD (LD)
(FWFT/SI)
n
TM
regardless of whether
0
- D
n
)
72V275
72V285
3
IDT
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standard mode or FWFT mode. The LD pin selects either a partial flag default
setting of 127 with parallel programming or a partial flag default setting of 1,023
with serial programming. The flags are updated according to the timing mode
and default offsets selected.
location of the memory. However, the timing mode, partial flag programming
method, and default or programmed offset settings existing before Partial Reset
remain unchanged. The flags are updated according to the timing mode and
offsets in effect. PRS is useful for resetting a device in mid-operation, when
reprogramming partial flags would be undesirable.
once. A LOW on the RT input during a rising RCLK edge initiates a retransmit
operation by setting the read pointer to the first location of the memory array.
automatically power down. Once in the power down state, the standby supply
current consumption is minimized. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.
CMOS technology.
MASTER RESET (MRS)
During Master Reset (MRS) the following events occur: The read and write
The Partial Reset (PRS) also sets the read and write pointers to the first
The Retransmit function allows data to be reread from the FIFO more than
If, at any time, the FIFO is not actively performing an operation, the chip will
The IDT72V275/72V285 are fabricated using IDT’s high speed submicron
READ CLOCK (RCLK)
READ ENABLE (REN)
RETRANSMIT (RT)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
HALF-FULL FLAG (HF)
DATA OUT (Q
OUTPUT ENABLE (OE)
0
- Q
n
COMMERCIAL AND INDUSTRIAL
)
TEMPERATURE RANGES
4512 drw 03