72V285L15TFI Integrated Device Technology (Idt), 72V285L15TFI Datasheet - Page 21

• Manufacturer Part Number: 72V285L15TFI
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 64K x 18 64-Pin STQFP Tray
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72V285L15TFI

• Package: 64STQFP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 1.125 Mb
• Organization: 64Kx18
• Data Bus Width: 18 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 3.3 V
• Operating Temperature: -40 to 85 °C

NOTES:
1. m = PAF offset .
2. D = maximum FIFO depth.
3. t
4. PAF is asserted and updated on the rising edge of WCLK only.
NOTE:
1. OE = LOW
D
Q
WCLK
RCLK
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO
32,768 x 18 and 65,536 x 18
WEN
0
0
REN
PAF
WCLK
In IDT Standard mode: D = 32,768 for the IDT72V275 and 65,536 for the IDT72V285.
In FWFT mode: D = 32,769 for the IDT72V275 and 65,537 for the IDT72V285.
RCLK and the rising edge of WCLK is less than t
SKEW2
RCLK
- D
- Q
WEN
REN
LD
15
15
LD
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t
t
CLKH
Figure 14. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
Figure 15. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
ENS
Figure 16. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
D - (m+1) words in FIFO
t
CLKL
t
ENH
SKEW2
DATA IN OUTPUT
, then the PAF deassertion time may be delayed one extra WCLK cycle.
t
REGISTER
CLKH
t
CLKH
1
TM
(2)
t
CLK
t
CLK
t
t
ENS
LDS
t
t
CLKL
DS
t
t
ENS
LDS
t
CLKL
OFFSET
PAE
2
21
t
PAF
t
t
t
ENH
DH
LDH
t
t
LDH
t
ENH
A
t
ENS
t
SKEW2
(3)
OFFSET
PAF
t
ENH
D - m words in FIFO
OFFSET
PAE
1
t
t
DH
t
ENH
LDH
t
t
LDH
ENH
t
A
COMMERCIAL AND INDUSTRIAL
(2)
PAF
). If the time between the rising edge of
TEMPERATURE RANGES
2
t
PAF
OFFSET
PAF
D-(m+1) words
in FIFO
4512 drw 19
4512 drw 17
4512 drw 18
(2)