72V285L15TFI Integrated Device Technology (Idt), 72V285L15TFI Datasheet - Page 22

• Manufacturer Part Number: 72V285L15TFI
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 64K x 18 64-Pin STQFP Tray
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72V285L15TFI

• Package: 64STQFP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 1.125 Mb
• Organization: 64Kx18
• Data Bus Width: 18 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 3.3 V
• Operating Temperature: -40 to 85 °C

NOTES:
1. For IDT Standard mode: D = maximum FIFO depth. D = 32,768 for the IDT72V275 and 65,536 for the IDT72V285.
2. For FWFT mode: D = maximum FIFO depth. D = 32,769 for the IDT72V275 and 65,537 for the IDT72V285.
WCLK
WCLK
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. t
5. PAE is asserted and updated on the rising edge of WCLK only.
RCLK
RCLK
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO
32,768 x 18 and 65,536 x 18
WEN
WEN
REN
REN
PAE
WCLK and the rising edge of RCLK is less than t
SKEW2
HF
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus t
t
CLKH
t
ENS
n words in FIFO
n+1 words in FIFO
Figure 17. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
t
CLKL
t
ENH
[
(2)
t
D-1
SKEW2
1
2
,
(3)
D/2 words in FIFO
Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes)
SKEW2
+ 1
(4)
]
, then the PAE deassertion may be delayed one extra RCLK cycle.
words in FIFO
t
t
PAE
CLKH
TM
(1)
2
,
(2)
t
ENS
t
CLKL
22
t
t
ENH
ENS
t
HF
n+1 words in FIFO
n+2 words in FIFO
t
ENS
[
D-1
D/2 + 1 words in FIFO
t
2
ENH
+ 2
]
(2)
(3)
words in FIFO
,
t
HF
1
(1)
,
(2)
COMMERCIAL AND INDUSTRIAL
PAE
). If the time between the rising edge of
t
PAE
[
D-1
2
TEMPERATURE RANGES
D/2 words in FIFO
2
+ 1
]
words in FIFO
n words in FIFO
n+1 words in FIFO
4512 drw 21
4512 drw 20
(1)
,
(2)
(2)
,
(3)