P87C552SBAA NXP Semiconductors, P87C552SBAA Datasheet - Page 31

• Manufacturer Part Number: P87C552SBAA
• Description: MCU 8-Bit 87C 80C51 CISC 8KB EPROM 3.3V/5V 68-Pin PLCC Tube
• Manufacturer: NXP Semiconductors

Specifications of P87C552SBAA

• Package: 68PLCC
• Device Core: 80C51
• Family Name: 87C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 40
• Interface Type: I2C/UART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Ram Size: 256 Byte
• Program Memory Size: 8 KB
• Program Memory Type: EPROM
• Operating Temperature: 0 to 70 °C

Philips Semiconductors
SIO1, I
transfer information between devices connected to the bus. The
main features of the bus are:
– Bidirectional data transfer between masters and slaves
– Multimaster bus (no central master)
– Arbitration between simultaneously transmitting masters without
– Serial clock synchronization allows devices with different bit rates
– Serial clock synchronization can be used as a handshake
– The I
The output latches of P1.6 and P1.7 must be set to logic 1 in order
to enable SIO1.
The 8XC552 on-chip I
the I
the low-speed mode) from and to the I
handles bytes transfer autonomously. It also keeps track of serial
transfers, and a status register (S1STA) reflects the status of SIO1
and the I
The CPU interfaces to the I
function registers: S1CON (SIO1 control register), S1STA (SIO1
status register), S1DAT (SIO1 data register), and S1ADR (SIO1
slave address register). The SIO1 logic interfaces to the external I
bus via two port 1 pins: P1.6/SCL (serial clock line) and P1.7/SDA
(serial data line).
A typical I
shows how a data transfer is accomplished on the bus. Depending
on the state of the direction bit (R/W), two types of data transfers are
possible on the I
1. Data transfer from a master transmitter to a slave receiver. The
2. Data transfer from a slave transmitter to a master receiver. The
The master device generates all of the serial clock pulses and the
START and STOP conditions. A transfer is ended with a STOP
condition or with a repeated START condition. Since a repeated
START condition is also the beginning of the next serial transfer, the
I
2003 Apr 01
2
C bus will not be released.
corruption of serial data on the bus
to communicate via one serial bus
mechanism to suspend and resume serial transfer
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I
capture/compare, high I/O, low voltage (2.7 V to 5.5 V), low power
first byte transmitted by the master is the slave address. Next
follows a number of data bytes. The slave returns an
acknowledge bit after each received byte.
first byte (the slave address) is transmitted by the master. The
slave then returns an acknowledge bit. Next follows the data
bytes transmitted by the slave to the master. The master returns
an acknowledge bit after all received bytes other than the last
byte. At the end of the last received byte, a “not acknowledge” is
returned.
2
C bus specification and supports all transfer modes (other than
2
2
C Serial I/O: The I
C bus may be used for test and diagnostic purposes
2
C bus.
2
C bus configuration is shown in Figure 32, and Figure 33
2
C bus:
2
C logic provides a serial interface that meets
2
2
C bus uses two wires (SDA and SCL) to
C logic via the following four special
2
C bus. The SIO1 logic
2
C, PWM,
2
C
31
Modes of Operation: The on-chip SIO1 logic may operate in the
following four modes:
1. Master Transmitter Mode:
2. Master Receiver Mode:
3. Slave Receiver Mode:
4. Slave Transmitter Mode:
In a given application, SIO1 may operate as a master and as a
slave. In the slave mode, the SIO1 hardware looks for its own slave
address and the general call address. If one of these addresses is
detected, an interrupt is requested. When the microcontroller wishes
to become the bus master, the hardware waits until the bus is free
before the master mode is entered so that a possible slave action is
not interrupted. If bus arbitration is lost in the master mode, SIO1
switches to the slave mode immediately and can detect its own
slave address in the same serial transfer.
Serial data output through P1.7/SDA while P1.6/SCL outputs the
serial clock. The first byte transmitted contains the slave address
of the receiving device (7 bits) and the data direction bit. In this
case the data direction bit (R/W) will be logic 0, and we say that
a “W” is transmitted. Thus the first byte transmitted is SLA+W.
Serial data is transmitted 8 bits at a time. After each byte is
transmitted, an acknowledge bit is received. START and STOP
conditions are output to indicate the beginning and the end of a
serial transfer.
The first byte transmitted contains the slave address of the
transmitting device (7 bits) and the data direction bit. In this case
the data direction bit (R/W) will be logic 1, and we say that an “R”
is transmitted. Thus the first byte transmitted is SLA+R. Serial
data is received via P1.7/SDA while P1.6/SCL outputs the serial
clock. Serial data is received 8 bits at a time. After each byte is
received, an acknowledge bit is transmitted. START and STOP
conditions are output to indicate the beginning and end of a
serial transfer.
Serial data and the serial clock are received through P1.7/SDA
and P1.6/SCL. After each byte is received, an acknowledge bit is
transmitted. START and STOP conditions are recognized as the
beginning and end of a serial transfer. Address recognition is
performed by hardware after reception of the slave address and
direction bit.
The first byte is received and handled as in the slave receiver
mode. However, in this mode, the direction bit will indicate that
the transfer direction is reversed. Serial data is transmitted via
P1.7/SDA while the serial clock is input through P1.6/SCL.
START and STOP conditions are recognized as the beginning
and end of a serial transfer.
P87C552
Product data