P87C552SBAA NXP Semiconductors, P87C552SBAA Datasheet - Page 32

• Manufacturer Part Number: P87C552SBAA
• Description: MCU 8-Bit 87C 80C51 CISC 8KB EPROM 3.3V/5V 68-Pin PLCC Tube
• Manufacturer: NXP Semiconductors

Specifications of P87C552SBAA

• Package: 68PLCC
• Device Core: 80C51
• Family Name: 87C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 40
• Interface Type: I2C/UART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Ram Size: 256 Byte
• Program Memory Size: 8 KB
• Program Memory Type: EPROM
• Operating Temperature: 0 to 70 °C

Philips Semiconductors
SIO1 Implementation and Operation: Figure 34 shows how the
on-chip I
describes the individual blocks.
I
The input filters have I
is less than 1.5V, the input logic level is interpreted as 0; if the input
voltage is greater than 3.0V, the input logic level is interpreted as 1.
Input signals are synchronized with the internal clock (f
spikes shorter than three oscillator periods are filtered out.
The output stages consist of open drain transistors that can sink
3mA at V
clamping diodes to V
bus and V
A
This 8-bit special function register may be loaded with the 7-bit slave
address (7 most significant bits) to which SIO1 will respond when
programmed as a slave transmitter or receiver. The LSB (GC) is
used to enable general call address (00H) recognition.
2003 Apr 01
NPUT
DDRESS
SDA
SCL
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I
capture/compare, high I/O, low voltage (2.7 V to 5.5 V), low power
CONDITION
F
ILTERS AND
START
2
OUT
R
C bus interface is implemented, and the following text
S
DD
EGISTER,
is switched off, the I
< 0.4V. These open drain outputs do not have
I
2
C bus
MSB
O
S
UTPUT
1
DD
1
2
ADR
C compatible input levels. If the input voltage
. Thus, if the device is connected to the I
SLAVE ADDRESS
S
TAGES
2
P1.7/SDA
2
C bus is not affected.
8XC554
P1.6/SCL
7
Figure 32. Typical I
DIRECTION
Figure 33. Data Transfer on the I
SIGNAL FROM RECEIVER
2
ACKNOWLEDGMENT
R/W
C, PWM,
BIT
8
OSC
/4), and
OTHER DEVICE WITH
ACK
9
I
2
R
2
C
P
C INTERFACE
32
2
C Bus Configuration
R
C
The comparator compares the received 7-bit slave address with its
own slave address (7 most significant bits in S1ADR). It also
compares the first received 8-bit byte with the general call address
(00H). If an equality is found, the appropriate status bits are set and
an interrupt is requested.
S
This 8-bit special function register contains a byte of serial data to
be transmitted or a byte which has just been received. Data in
S1DAT is always shifted from right to left; the first bit to be
transmitted is the MSB (bit 7) and, after a byte has been received,
the first bit of received data is located at the MSB of S1DAT. While
data is being shifted out, data on the bus is simultaneously being
shifted in; S1DAT always contains the last byte present on the bus.
Thus, in the event of lost arbitration, the transition from master
transmitter to slave receiver is made with the correct data in S1DAT.
P
HIFT
OMPARATOR
V
1
CLOCK LINE HELD LOW WHILE
INTERRUPTS ARE SERVICED
DD
R
EGISTER,
REPEATED IF MORE BYTES
ARE TRANSFERRED
2
C Bus
2
S
OTHER DEVICE WITH
1
DAT
SIGNAL FROM RECEIVER
I
2
3–8
C INTERFACE
ACKNOWLEDGMENT
ACK
9
SU00964
SDA
SCL
P/S
P87C552
Product data
CONDITION
CONDITION
REPEATED
SU00965
START
STOP