LC4256V-75TN100E LATTICE SEMICONDUCTOR, LC4256V-75TN100E Datasheet - Page 48

• Manufacturer Part Number: LC4256V-75TN100E
• Description: CPLD ispMACH® 4000V Family 256 Macro Cells 168MHz EECMOS Technology 3.3V 100-Pin TQFP
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LC4256V-75TN100E

• Package: 100TQFP
• Family Name: ispMACH® 4000V
• Number Of Macro Cells: 256
• Maximum Propagation Delay Time: 7.5 ns
• Number Of User I/os: 64
• Number Of Logic Blocks/elements: 36
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 168 MHz
• Number Of Product Terms Per Macro: 80
• Memory Type: EEPROM
• Operating Temperature: -40 to 130 °C

Lattice Semiconductor
ispMACH 4032Z and 4064Z Logic Signal Connections: 56-Ball csBGA (Cont.)
1. For device migration considerations, these NC pins are input signal pins in ispMACH 4064Z devices.
Ball Number
G10
K10
H10
E10
D10
C10
B10
A10
F10
J10
H6
H7
H8
G8
D8
C8
C7
C6
C5
C4
K5
K6
K7
K8
K9
F8
E8
A9
A8
A7
A6
A5
A4
A3
A2
A1
Bank Number
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
-
-
-
-
VCCO (Bank 1)
GND (Bank 1)
GLB/MC/Pad
B15/GOE1
A0/GOE0
CLK1/I
CLK2/I
CLK3/I
CLK0/I
TMS
VCC
GND
TDO
A15
NC
NC
B10
B11
NC
NC
B12
B13
B14
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
A1
A2
A3
A4
1
1
1
1
ispMACH 4032Z
48
ispMACH 4000V/B/C/Z Family Data Sheet
A^15
B^10
B^11
B^12
B^13
B^14
B^15
ORP
B^0
B^1
B^2
B^3
B^4
B^5
B^6
B^7
B^8
B^9
A^0
A^1
A^2
A^3
A^4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VCCO (Bank 1)
GND (Bank 1)
GLB/MC/Pad
D0/GOE1
A0/GOE0
CLK1/I
CLK2/I
CLK3/I
CLK0/I
GND
TMS
TDO
VCC
C10
C11
D15
D12
D10
B0
C0
C1
C2
C4
C6
C8
D8
D6
D4
D2
A1
A2
A4
A6
I
I
I
I
1
1
1
1
ispMACH 4064Z
ORP
B^0
C^0
C^1
C^2
C^3
C^4
C^5
C^6
C^7
D^7
D^6
D^5
D^4
D^3
D^2
D^1
D^0
A^0
A^1
A^2
A^3
A^4
-
-
-
-
-
-
-
-
-
-
-
-
-
-