XC3SD3400A-4CSG484I Xilinx Inc, XC3SD3400A-4CSG484I Datasheet - Page 100

• Manufacturer Part Number: XC3SD3400A-4CSG484I
• Description: FPGA Spartan®-3A Family 3.4M Gates 53712 Cells 667MHz 90nm Technology 1.2V 484-Pin LCSBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A DSPr

Specifications of XC3SD3400A-4CSG484I

• Package: 484LCSBGA
• Family Name: Spartan®-3A
• Device Logic Units: 53712
• Device System Gates: 3400000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 309
• Ram Bits: 2322432
• Number Of Logic Elements/cells: 53712
• Number Of Labs/clbs: 5968
• Total Ram Bits: 2322432
• Number Of I /o: 309
• Number Of Gates: 3400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA, CSPBGA
• No. Of Logic Blocks: 5968
• No. Of Gates: 3400000
• No. Of Macrocells: 53712
• Family Type: Spartan-3A
• No. Of Speed Grades: 4
• No. Of I/o's: 309
• Clock Management: DCM
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1532 - KIT DEVELOPMENT SPARTAN 3ADSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 70: FG676 Footprint Migration Differences (Cont’d)
Migration Recommendations
There are multiple pinout differences between the XC3SD1800A and the XC3SD3400A FPGAs in the FG676 package.
Please note the differences between the two devices from
DS610 (v3.0) October 4, 2010
Product Specification
FG676
AD23
AC18
AB10
AB17
AB20
AA19
AC22
W18
AD5
Ball
Y11
Y18
Y19
AF2
AF7
AC5
AC7
AA8
AB3
AB4
AA4
AA5
H4
G1
G2
G5
D1
D2
C1
C2
Y8
Y3
Y4
IP_2/VREF_2
XC3S1400A
IP_L12N_3/
IP_L04N_3/
IP_L58N_3/
IP_L54N_3
IP_L16N_3
IP_L08N_3
IP_L62N_3
IP_L54P_3
IP_L16P_3
IP_L12P_3
IP_L08P_3
IP_L04P_3
IP_L62P_3
IP_L58P_3
VREF_3
VREF_3
VREF_3
Type
N.C.
IP_2
N.C.
N.C.
N.C.
IP_2
IP_2
N.C.
N.C.
N.C.
IP_2
IP_2
IP_2
IP_2
N.C.
IP_2
N.C.
Spartan-3A
XC3S1400A
Bank
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
XC3SD1800A
IP_2/VREF_2
IP_2/VREF_2
IP_L12N_3/
IP_L04N_3/
IP_L58N_3/
IP_L54N_3
IP_L16N_3
IP_L08N_3
IP_L62N_3
IP_L54P_3
IP_L16P_3
IP_L12P_3
IP_L08P_3
IP_L04P_3
IP_L62P_3
IP_L58P_3
VREF_3
VREF_3
VREF_3
Type
IO_2
IP_2
IP_2
IP_2
IP_2
IP_2
IP_2
IP_2
IP_2
IP_2
IP_2
IP_2
IP_2
IP_2
IP_2
IP_2
Spartan-3A DSP
www.xilinx.com
Table 70
XC3SD1800A
Bank
Spartan-3A DSP FPGA Family: Pinout Descriptions
and take the necessary precautions.
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
2
2
3
3
3
3
3
3
3
3
3
XC3SD3400A
IP_3/VREF_3
IP_3/VREF_3
IP_3/VREF_3
VCCAUX
VCCAUX
VCCO_2
VCCAUX
VCCO_3
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
Type
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
IO_2
IP_3
IP_3
Spartan-3A DSP
XC3SD3400A
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
Bank
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
2
2
3
3
3
3
3
3
FG676
AD23
AC18
AB10
AB17
AB20
AA19
AC22
W18
AD5
Ball
Y11
AF2
AF7
AC5
AC7
AA8
AB3
AB4
AA4
AA5
Y18
Y19
H4
G1
G2
G5
D1
D2
C1
C2
Y8
Y3
Y4
100