XC3SD3400A-4CSG484I Xilinx Inc, XC3SD3400A-4CSG484I Datasheet - Page 97

• Manufacturer Part Number: XC3SD3400A-4CSG484I
• Description: FPGA Spartan®-3A Family 3.4M Gates 53712 Cells 667MHz 90nm Technology 1.2V 484-Pin LCSBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A DSPr

Specifications of XC3SD3400A-4CSG484I

• Package: 484LCSBGA
• Family Name: Spartan®-3A
• Device Logic Units: 53712
• Device System Gates: 3400000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 309
• Ram Bits: 2322432
• Number Of Logic Elements/cells: 53712
• Number Of Labs/clbs: 5968
• Total Ram Bits: 2322432
• Number Of I /o: 309
• Number Of Gates: 3400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA, CSPBGA
• No. Of Logic Blocks: 5968
• No. Of Gates: 3400000
• No. Of Macrocells: 53712
• Family Type: Spartan-3A
• No. Of Speed Grades: 4
• No. Of I/o's: 309
• Clock Management: DCM
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1532 - KIT DEVELOPMENT SPARTAN 3ADSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS610 (v3.0) October 4, 2010
Product Specification
FG676 Footprint –
XC3SD3400A FPGA
Left Half of Package
(Top View)
314
100
34
51
37
32
40
36
24
2
2
4
Note:
question marks inside
indicate pin differences
from the XC3SD1800A
device. Please see the
Footprint Migration
Differences
information.
I/O: Unrestricted,
general-purpose user I/O.
INPUT: Unrestricted,
general-purpose input pin.
DUAL: Configuration pins,
then possible user I/O.
VREF: User I/O or input
voltage reference for bank.
CLK: User I/O, input, or
clock buffer input.
CONFIG: Dedicated
configuration pins.
SUSPEND: Dedicated
SUSPEND and
dual-purpose AWAKE
Power Management pins
JTAG: Dedicated JTAG
port pins.
GND: Ground
VCCO: Output voltage
supply for bank.
VCCINT: Internal core
supply voltage (+1.2V).
VCCAUX: Auxiliary supply
voltage.
The boxes with
section for more
Figure 17: FG676 Package Footprint for XC3SD3400A FPGA (Top View–Left Half)
A
B
C
D
E
G
H
K
M
N
P
R
U
W
F
J
L
T
V
Y
A
A
A
B
A
C
A
D
A
E
A
F
VCCAUX
INPUT
VREF_3
INPUT
INPUT
INPUT
VREF_3
LHCLK2
VREF_3
L02N_3
L11P_3
L17N_3
L24P_3
L24N_3
L29N_3
L31P_3
L33P_3
L36P_3
L44P_3
INPUT
INPUT
L47P_3
L50P_3
L53P_3
L60P_3
L60N_3
L65P_3
L66P_3
www.xilinx.com
GND
GND
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
∇
∇
∇
I/O
I/O
I/O
I/O
I/O
1
PROG_
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VREF_3
LHCLK3
VCCO_3
VCCAUX
L11N_3
INPUT
L20N_3
L23N_3
L31N_3
L33N_3
L36N_3
L44N_3
VREF_3
VREF_3
L02P_3
L17P_3
L29P_3
L47N_3
INPUT
L50N_3
L53N_3
L55P_3
L64P_3
L65N_3
INPUT
L66N_3
IRDY2
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
∇
∇
∇
I/O
I/O
I/O
I/O
I/O
∇
2
B
INPUT
LHCLK5
INPUT
L51P_0
L51N_0
L06P_3
L07P_3
L14N_3
L14P_3
L20P_3
L23P_3
L25N_3
L27N_3
L34N_3
L37P_3
L38P_3
L46P_3
INPUT
L52P_3
L55N_3
L64N_3
L06P_2
L06N_2
GND
GND
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
∇
∇
3
Spartan-3A DSP FPGA Family: Pinout Descriptions
VCCINT
VCCINT
VCCAUX
VREF_3
LHCLK4
L45P_0
L45N_0
L06N_3
L07N_3
L09N_3
INPUT
L19N_3
L22N_3
L25P_3
L27P_3
L30N_3
L34P_3
L37N_3
L38N_3
L42N_3
INPUT
L46N_3
L52N_3
L01P_2
L01N_2
L07P_2
L07N_2
TMS
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
∇
∇
I/O
I/O
I/O
I/O
I/O
∇
∇
∇
M1
M0
4
VCCINT
VCCAUX
VCCAUX
VCCO_0
VCCO_3
VCCO_3
VCCO_3
VCCAUX
VCCO_2
VREF_3
L44P_0
L09P_3
L19P_3
L22P_3
L28P_3
L30P_3
L40P_3
L42P_3
L49P_3
L49N_3
L57P_3
INPUT
L10P_2
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
∇
I/O
I/O
I/O
∇
∇
∇
∇
∇
5
VCCINT
LHCLK0
VREF_2
L41P_0
L41N_0
L44N_0
L03P_3
L10N_3
L13N_3
L18P_3
L28N_3
L32P_3
L39N_3
L40N_3
L51N_3
INPUT
L59N_3
L63N_3
L57N_3
L08P_2
L08N_2
L10N_2
GND
GND
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
∇
I/O
I/O
I/O
I/O
I/O
I/O
6
VCCO_0
VREF_0
LHCLK1
VCCO_2
L42P_0
L42N_0
INPUT
L48N_0
L48P_0
L03N_3
L10P_3
L13P_3
L18N_3
L26N_3
L32N_3
L39P_3
L45N_3
L51P_3
L56P_3
L59P_3
L63P_3
L02P_2
L02N_2
CSO_B
L14N_2
L11P_2
L11N_2
GND
TDI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
∇
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M2
∇
∇
7
Bank 2
Bank 0
PUDC_B
VCCINT
VCCINT
VCCO_0
VREF_0
VCCO_3
VCCO_3
VCCO_2
L38P_0
L38N_0
L40P_0
L40N_0
L52P_0
L52N_0
L01P_3
L05N_3
L26P_3
L41P_3
L45P_3
L56N_3
L61N_3
L18N_2
L14P_2
L18P_2
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
∇
∇
8
VCCAUX
VCCAUX
LHCLK6
VREF_2
L36P_0
L36N_0
L37N_0
L47P_0
L47N_0
L01N_3
L05P_3
L15N_3
L21N_3
L35P_3
L41N_3
L43N_3
L48N_3
L61P_3
INPUT
INPUT
TRDY2
L05P_2
L05N_2
L15P_2
L15N_2
L19P_2
L19N_2
GND
GND
VS1
VS0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
∇
∇
I/O
I/O
I/O
I/O
I/O
I/O
9
VCCINT
VCCAUX
LHCLK7
VREF_3
L33N_0
L34N_0
L46N_0
INPUT
L35N_3
VREF_2
L33P_0
L34P_0
L37P_0
L46P_0
L15P_3
L21P_3
L43P_3
L48P_3
L09P_2
L09N_2
L12P_2
L12N_2
INPUT
INPUT
L22P_2
L22N_2
GND
GND
GND
10
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
∇
I/O
I/O
I/O
I/O
I/O
I/O
∇
D7
D6
VCCINT
VCCINT
VCCINT
VCCINT
VCCO_0
VREF_0
VREF_0
VCCO_0
VCCAUX
INPUT
INPUT
VCCO_2
VCCO_2
L32P_0
L32N_0
L43P_0
L43N_0
L13N_2
L23N_2
L13P_2
L23P_2
GND
GND
GND
GND
GND
GND
GND
I/O
11
I/O
I/O
I/O
I/O
I/O
I/O
I/O
∇
VCCINT
VCCINT VCCINT
VCCINT
VCCINT
RDWR_B
L29P_0
L29N_0
L30N_0
INPUT
L31P_0
L31N_0
L35P_0
L35N_0
L39P_0
L39N_0
INPUT
VREF_2
L16P_2
L16N_2
L17P_2
L17N_2
L21P_2
L21N_2
L24N_2
L24P_2
GND
GND
GND
12
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VS2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D4
D5
VCCINT
VCCINT
VCCINT
VCCO_0
VCCAUX
GCLK10
GCLK11
INPUT
L28N_0
L27N_0
INPUT
INPUT
GCLK13
GCLK12
GCLK15
GCLK14
L28P_0
L30P_0
L27P_0
GCLK8
GCLK9
L20P_2
L20N_2
L25N_2
L25P_2
INPUT
INPUT
L26N_2
L26P_2
GND
GND
GND
GND
13
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
97