XC3SD3400A-4CSG484I Xilinx Inc, XC3SD3400A-4CSG484I Datasheet - Page 14

• Manufacturer Part Number: XC3SD3400A-4CSG484I
• Description: FPGA Spartan®-3A Family 3.4M Gates 53712 Cells 667MHz 90nm Technology 1.2V 484-Pin LCSBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A DSPr

Specifications of XC3SD3400A-4CSG484I

• Package: 484LCSBGA
• Family Name: Spartan®-3A
• Device Logic Units: 53712
• Device System Gates: 3400000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 309
• Ram Bits: 2322432
• Number Of Logic Elements/cells: 53712
• Number Of Labs/clbs: 5968
• Total Ram Bits: 2322432
• Number Of I /o: 309
• Number Of Gates: 3400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA, CSPBGA
• No. Of Logic Blocks: 5968
• No. Of Gates: 3400000
• No. Of Macrocells: 53712
• Family Type: Spartan-3A
• No. Of Speed Grades: 4
• No. Of I/o's: 309
• Clock Management: DCM
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1532 - KIT DEVELOPMENT SPARTAN 3ADSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Single-Ended I/O Standards
Table 10: Recommended Operating Conditions for User I/Os Using Single-Ended Standards
DS610 (v3.0) October 4, 2010
Product Specification
Notes:
1.
2.
3.
4.
5.
6.
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33_3
PCI66_3
HSTL_I
HSTL_III
HSTL_I_18
HSTL_II_18
HSTL_III_18
SSTL18_I
SSTL18_II
SSTL2_I
SSTL2_II
SSTL3_I
SSTL3_II
IOSTANDARD
Descriptions of the symbols used in this table are as follows:
V
V
V
V
In general, the V
and for PCI I/O standards.
For device operation, the maximum signal voltage (V
There is approximately 100 mV of hysteresis on inputs using LVCMOS33 and LVCMOS25 I/O standards.
All Dedicated pins (PROG_B, DONE, SUSPEND, TCK, TDI, TDO, and TMS) draw power from the V
LVCMOS33 standard depending on V
using these pins as part of a standard 2.5V configuration interface, apply 2.5V to the V
throughout configuration.
For information on PCI IP solutions, see www.xilinx.com/pci. The PCI IOSTANDARD is not supported on input-only pins. The PCIX
IOSTANDARD is available and has equivalent characteristics but no PCI-X IP is supported.
CCO
REF
IL
IH
Attribute
—the input voltage that indicates a Low logic level
—the input voltage that indicates a High logic level
(6)
(6)
—the reference voltage for setting the input switching threshold
—the supply voltage for output drivers
(4)
(4,5)
CCO
rails supply only output drivers, not input circuits. The exceptions are for LVCMOS25 inputs when V
Min (V)
1.65
3.0
3.0
2.3
1.4
1.1
3.0
3.0
1.4
1.4
1.7
1.7
1.7
1.7
1.7
2.3
2.3
3.0
3.0
V
CCO
Nom (V)
for Drivers
CCAUX
3.3
3.3
2.5
1.8
1.5
1.2
3.3
3.3
1.5
1.5
1.8
1.8
1.8
1.8
1.8
2.5
2.5
3.3
3.3
. The Dual-Purpose configuration pins use the LVCMOS standard before the User mode. When
(2)
Max (V)
1.95
3.6
3.6
2.7
1.6
1.3
3.6
3.6
1.6
1.6
1.9
1.9
1.9
1.9
1.9
2.7
2.7
3.6
3.6
IH
max) can be as high as V
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
www.xilinx.com
Min (V)
0.833
0.833
0.68
1.13
1.13
0.8
1.3
1.3
–
–
–
V
these I/O standards
REF
Nom (V)
is not used for
0.900
0.900
V
0.75
1.25
1.25
0.9
0.9
0.9
1.1
1.5
1.5
REF
IN
max. See
CCO
Max (V)
lines of Banks 0, 1, and 2 at power-on as well as
0.969
0.969
1.38
1.38
0.9
1.1
1.7
1.7
–
–
–
Table
7.
CCAUX
V
V
V
V
0.3 • V
0.3 • V
V
V
V
V
V
V
V
REF
REF
REF
REF
Max (V)
REF
REF
REF
REF
REF
REF
REF
rail and use the LVCMOS25 or
V
0.8
0.8
0.7
0.4
0.4
0.4
– 0.125
– 0.125
– 0.150
– 0.150
IL
– 0.1
– 0.1
– 0.1
– 0.1
– 0.1
– 0.2
– 0.2
CCO
CCO
CCAUX
V
V
V
V
0.5 • V
0.5 • V
V
V
V
V
V
V
V
REF
REF
REF
REF
Min (V)
REF
REF
REF
REF
REF
REF
REF
= 3.3V range
V
2.0
2.0
1.7
0.8
0.8
0.7
+ 0.125
+ 0.125
+ 0.150
+ 0.150
IH
+ 0.1
+ 0.1
+ 0.1
+ 0.1
+ 0.1
+ 0.2
+ 0.2
CCO
CCO
(3)
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