XC3SD3400A-4CSG484I Xilinx Inc, XC3SD3400A-4CSG484I Datasheet - Page 19

• Manufacturer Part Number: XC3SD3400A-4CSG484I
• Description: FPGA Spartan®-3A Family 3.4M Gates 53712 Cells 667MHz 90nm Technology 1.2V 484-Pin LCSBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A DSPr

Specifications of XC3SD3400A-4CSG484I

• Package: 484LCSBGA
• Family Name: Spartan®-3A
• Device Logic Units: 53712
• Device System Gates: 3400000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 309
• Ram Bits: 2322432
• Number Of Logic Elements/cells: 53712
• Number Of Labs/clbs: 5968
• Total Ram Bits: 2322432
• Number Of I /o: 309
• Number Of Gates: 3400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA, CSPBGA
• No. Of Logic Blocks: 5968
• No. Of Gates: 3400000
• No. Of Macrocells: 53712
• Family Type: Spartan-3A
• No. Of Speed Grades: 4
• No. Of I/o's: 309
• Clock Management: DCM
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1532 - KIT DEVELOPMENT SPARTAN 3ADSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Characteristics
All Spartan-3A DSP FPGAs ship in two speed grades: –4
and the higher performance –5. Switching characteristics in
this document are designated as Advance, Preliminary, or
Production, as shown in
as follows:
Advance: These specifications are based on simulations
only and are typically available soon after establishing
FPGA specifications. Although speed grades with this
designation are considered relatively stable and
conservative, some under-reporting might still occur.
Preliminary: These specifications are based on complete
early silicon characterization. Devices and speed grades
with this designation are intended to give a better indication
of the expected performance of production silicon. The
probability of under-reporting preliminary delays is greatly
reduced compared to Advance data.
Production: These specifications are approved once
enough production silicon of a particular device family
member has been characterized to provide full correlation
between speed files and devices over numerous production
lots. There is no under-reporting of delays, and customers
receive formal notification of any subsequent changes.
Typically, the slowest speed grades transition to Production
before faster speed grades.
Software Version Requirements
Production-quality systems must use FPGA designs
compiled using a speed file designated as PRODUCTION
status. FPGAs designs using a less mature speed file
designation should only be used during system prototyping
or pre-production qualification. FPGA designs with speed
files designated as Preview, Advance, or Preliminary should
not be used in a production-quality system.
Whenever a speed file designation changes, as a device
matures toward Production status, rerun the latest Xilinx®
ISE® software on the FPGA design to ensure that the
FPGA design incorporates the latest timing information and
software updates.
Production designs will require updating the Xilinx ISE
development software with a future version and/or Service
Pack.
All parameter limits are representative of worst-case supply
voltage and junction temperature conditions. Unless
otherwise noted, the published parameter values apply
to all Spartan-3A DSP devices. AC and DC
characteristics are specified using the same numbers
for both commercial and industrial grades.
DS610 (v3.0) October 4, 2010
Product Specification
Table
15. Each category is defined
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
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•
Timing parameters and their representative values are
selected for inclusion below either because they are
important as general design requirements or they indicate
fundamental device performance characteristics. The
Spartan-3A DSP FPGA speed files (v1.32), part of the
Xilinx Development Software, are the original source for
many but not all of the values. The speed grade
designations for these files are shown in
complete, more precise, and worst-case data, use the
values reported by the Xilinx static timing analyzer (TRACE
in the Xilinx development software) and back-annotated to
the simulation netlist.
Table 15: Spartan-3A DSP v1.32 Speed Grade
Designations
Table 16
FPGA speed files.
Table 16: Spartan-3A DSP Speed File Version History
XC3SD1800A
XC3SD3400A
Version
1.32
1.31
1.30
1.29
1.28
1.27
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Device
provides the recent history of the Spartan-3A DSP
ISE 10.1.02
ISE 10.1
ISE 9.2.03i
ISE 9.2.01i
ISE 9.2i
ISE 9.1.03i
Release
ISE
Advance
Updated DSP timing model to reflect
higher performance for some
implementations
Added Automotive support
Added absolute minimum values
Production Speed Files for -4 and -5
speed grades
Minor updates
Advance Speed Files for -4 speed grade
Preliminary
Description
Table
15. For more
Production
-4, -5
-4, -5
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