XC3SD3400A-4CSG484I Xilinx Inc, XC3SD3400A-4CSG484I Datasheet - Page 2

• Manufacturer Part Number: XC3SD3400A-4CSG484I
• Description: FPGA Spartan®-3A Family 3.4M Gates 53712 Cells 667MHz 90nm Technology 1.2V 484-Pin LCSBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A DSPr

Specifications of XC3SD3400A-4CSG484I

• Package: 484LCSBGA
• Family Name: Spartan®-3A
• Device Logic Units: 53712
• Device System Gates: 3400000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 309
• Ram Bits: 2322432
• Number Of Logic Elements/cells: 53712
• Number Of Labs/clbs: 5968
• Total Ram Bits: 2322432
• Number Of I /o: 309
• Number Of Gates: 3400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA, CSPBGA
• No. Of Logic Blocks: 5968
• No. Of Gates: 3400000
• No. Of Macrocells: 53712
• Family Type: Spartan-3A
• No. Of Speed Grades: 4
• No. Of I/o's: 309
• Clock Management: DCM
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1532 - KIT DEVELOPMENT SPARTAN 3ADSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS610 (v3.0) October 4, 2010
Introduction
The Spartan®-3A DSP family of Field-Programmable Gate Arrays
(FPGAs) solves the design challenges in most high- volume,
cost-sensitive, high-performance DSP applications. The
two-member family offers densities ranging from 1.8 to 3.4 million
system gates, as shown in
The Spartan-3A DSP family builds on the success of the
Spartan-3A FPGA family by increasing the amount of memory per
logic and adding XtremeDSP™ DSP48A slices. New features
improve system performance and reduce the cost of configuration.
These Spartan-3A DSP FPGA enhancements, combined with
proven 90 nm process technology, deliver more functionality and
bandwidth per dollar than ever before, setting the new standard in
the programmable logic and DSP processing industry.
The Spartan-3A DSP FPGAs extend and enhance the Spartan-3A
FPGA family. The XC3SD1800A and the XC3SD3400A devices
are tailored for DSP applications and have additional block RAM
and XtremeDSP DSP48A slices. The XtremeDSP DSP48A slices
replace the 18x18 multipliers found in the Spartan-3A devices and
are based on the DSP48 blocks found in the Virtex®-4 devices.
The block RAMs are also enhanced to run faster by adding an
output register. Both the block RAM and DSP48A slices in the
Spartan-3A DSP devices run at 250 MHz in the lowest cost,
standard -4 speed grade.
Because of their exceptional DSP price/performance ratio,
Spartan-3A DSP FPGAs are ideally suited to a wide range of
consumer electronics applications, such as broadband access,
home networking, display/projection, and digital television.
The Spartan-3A DSP family is a superior alternative to mask
programmed ASICs. FPGAs avoid the high initial cost, lengthy
development cycles, and the inherent inflexibility of conventional
ASICs. Also, FPGA programmability permits design upgrades in
the field with no hardware replacement necessary, an impossibility
with ASICs.
Features
•
•
Table 1: Summary of Spartan-3A DSP FPGA Attributes
XC3SD1800A
XC3SD3400A
Notes:
1.
© Copyright 2007–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS610 (v3.0) October 4, 2010
Product Specification
Device
Very low cost, high-performance DSP solution for
high-volume, cost-conscious applications
250 MHz XtremeDSP DSP48A Slices
•
•
•
•
•
•
By convention, one Kb is equivalent to 1,024 bits.
Dedicated 18-bit by 18-bit multiplier
Available pipeline stages for enhanced performance of at
least 250 MHz in the standard -4 speed grade
48-bit accumulator for multiply-accumulate (MAC) operation
Integrated adder for complex multiply or multiply-add
operation
Integrated 18-bit pre-adder
Optional cascaded Multiply or MAC
System
1800K
3400K
Gates
Logic Cells
Equivalent
37,440
53,712
Table
1.
CLB Array (One CLB = Four Slices) Distributed
Rows Columns
104
88
6
48
58
CLBs
4,160
5,968
Total
www.xilinx.com
Introduction and Ordering Information
16,640
23,872
Slices
Total
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•
•
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•
•
•
•
•
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260K
373K
RAM
Hierarchical SelectRAM™ memory architecture
•
•
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Dual-range V
Suspend, Hibernate modes reduce system power
Low-power option reduces quiescent current
Multi-voltage, multi-standard SelectIO™ interface pins
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•
•
•
•
•
•
•
•
•
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Abundant, flexible logic resources
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•
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Eight Digital Clock Managers (DCMs)
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•
•
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Eight low-skew global clock networks, eight additional clocks
per half device, plus abundant low-skew routing
Configuration interface to industry-standard PROMs
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MicroBlaze™ and PicoBlaze™ embedded processor cores
BGA and CSP packaging with Pb-free options
•
XA Automotive
Bits
Spartan-3A DSP FPGA Family:
(1)
Up to 2268 Kbits of fast block RAM with byte write enables
for processor applications
Up to 373 Kbits of efficient distributed RAM
Registered outputs on the block RAM with operation of at
least 280 MHz in the standard -4 speed grade
Up to 519 I/O pins or 227 differential signal pairs
LVCMOS, LVTTL, HSTL, and SSTL single-ended I/O
3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
Selectable output drive, up to 24 mA per pin
QUIETIO standard reduces I/O switching noise
Full 3.3V ± 10% compatibility and hot swap compliance
622+ Mb/s data transfer rate per differential I/O
LVDS, RSDS, mini-LVDS, HSTL/SSTL differential I/O with
integrated differential termination resistors
Enhanced Double Data Rate (DDR) support
DDR/DDR2 SDRAM support up to 333 Mb/s
Fully compliant 32-/64-bit, 33/66 MHz PCI support
Densities up to 53712 logic cells, including optional shift
register
Efficient wide multiplexers, wide logic, fast carry logic
IEEE 1149.1/1532 JTAG programming/debug port
Clock skew elimination (delay locked loop)
Frequency synthesis, multiplication, division
High-resolution phase shifting
Wide frequency range (5 MHz to over 320 MHz)
Low-cost, space-saving SPI serial Flash PROM
x8 or x8/x16 BPI parallel NOR Flash PROM
Low-cost Xilinx®
Unique Device DNA identifier for design authentication
Load multiple bitstreams under FPGA control
Post-configuration CRC checking
Common footprints support easy density migration
1512K
2268K
Block
RAM
Bits
CCAUX
(1)
version available
DSP48As
supply simplifies 3.3V-only design
Platform Flash
126
84
DCMs
8
8
Product Specification
with JTAG
Maximum
User I/O
519
469
Differential
Maximum
I/O Pairs
227
213
2