MT48LC16M8A2TG-75:G Micron Technology Inc, MT48LC16M8A2TG-75:G Datasheet - Page 2

• Manufacturer Part Number: MT48LC16M8A2TG-75:G
• Description: DRAM Chip SDRAM 128M-Bit 16Mx8 3.3V 54-Pin TSOP-II Tray
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC16M8A2TG-75:G

• Package: 54TSOP-II
• Density: 128 Mb
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Clock Rate: 133 MHz
• Maximum Random Access Time: 6|5.4 ns
• Operating Temperature: 0 to 70 °C

Table 3:
General Description
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM_1.fm - Rev. N 1/09 EN
128Mb SDRAM Part Numbers
Notes:
1. FBGA Device Decode: http://www.micron.com/support/FBGA/FBGA.asp
The Micron
containing 134,217,728 bits. It is internally configured as a quad-bank DRAM with a
synchronous interface (all signals are registered on the positive edge of the clock signal,
CLK). Each of the x4’s 33,554,432-bit banks is organized as 4,096 rows by 2,048 columns
by 4 bits. Each of the x8’s 33,554,432-bit banks is organized as 4,096 rows by 1,024
columns by 8 bits. Each of the x16’s 33,554,432-bit banks is organized as 4,096 rows by
512 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select
the bank; A0–A11 select the row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable read or write burst lengths of 1, 2, 4, or 8 loca-
tions, or the full page, with a burst terminate option. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at the end of the burst
sequence.
The 128Mb SDRAM uses an internal pipelined architecture to achieve high-speed opera-
tion. This architecture is compatible with the 2n rule of prefetch architectures, but it also
allows the column address to be changed on every clock cycle to achieve a high-speed,
fully random access. Precharging one bank while accessing one of the other three banks
will hide the precharge cycles and provide seamless high-speed, random-access opera-
tion.
The 128Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh
mode is provided along with a power-saving, power-down mode. All inputs and outputs
are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operating performance, including the
ability to synchronously burst data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks to hide precharge time, and
the capability to randomly change column addresses on each clock cycle during a burst
access.
Part Number
MT48LC32M4A2TG
MT48LC32M4A2P
MT48LC16M8A2TG
MT48LC16M8A2P
MT48LC16M8A2FB
MT48LC16M8A2BB
MT48LC8M16A2TG
MT48LC8M16A2P
MT48LC8M16A2B4
MT48LC8M16A2F4
®
128Mb SDRAM is a high-speed CMOS, dynamic random access memory
1
1
1
1
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb: x4, x8, x16 SDRAM
General Description
©1999 Micron Technology, Inc. All rights reserved.
Architecture
32 Meg x 4
32 Meg x 4
16 Meg x 8
16 Meg x 8
16 Meg x 8
16 Meg x 8
8 Meg x 16
8 Meg x 16
8 Meg x 16
8 Meg x 16