MT48LC16M8A2TG-75:G Micron Technology Inc, MT48LC16M8A2TG-75:G Datasheet - Page 65

• Manufacturer Part Number: MT48LC16M8A2TG-75:G
• Description: DRAM Chip SDRAM 128M-Bit 16Mx8 3.3V 54-Pin TSOP-II Tray
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC16M8A2TG-75:G

• Package: 54TSOP-II
• Density: 128 Mb
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Clock Rate: 133 MHz
• Maximum Random Access Time: 6|5.4 ns
• Operating Temperature: 0 to 70 °C

Figure 49:
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM_2.fm - Rev. N 1/09 EN
DQML, DQMH
COMMAND
A0–A9, A11
BA0, BA1
DQM /
CKE
CLK
A10
DQ
t CMS
t CKS
t AS
t AS
t AS
ACTIVE
T0
ROW
ROW
BANK
WRITE – Without Auto Precharge
t CKH
t CMH
t AH
t AH
t AH
Notes:
t RCD
t RAS
t RC
t CK
T1
NOP
1. For this example, BL = 4, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 15ns is required between <D
3. x16: A9 and A11 = “Don’t Care.”
DISABLE AUTO PRECHARGE
quency.
x8: A11 = “Don’t Care.”
t CMS
t CL
t DS
COLUMN m 3
WRITE
BANK
T2
D
IN
t CMH
t CH
t DH
m
t DS
D
T3
IN
NOP
m + 1
t DH
t DS
D
IN
T4
NOP
m + 2
t DH
65
IN
m + 3> and the PRECHARGE command, regardless of fre-
t DS
D
IN
T5
NOP
m + 3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t DH
t WR
NOP
T6
2
128Mb: x4, x8, x16 SDRAM
SINGLE BANK
PRECHARGE
ALL BANKS
BANK
T7
©1999 Micron Technology, Inc. All rights reserved.
Timing Diagrams
t RP
NOP
T8
ACTIVE
ROW
ROW
BANK
T9
DON’T CARE