MT48LC16M8A2TG-75:G Micron Technology Inc, MT48LC16M8A2TG-75:G Datasheet - Page 32

• Manufacturer Part Number: MT48LC16M8A2TG-75:G
• Description: DRAM Chip SDRAM 128M-Bit 16Mx8 3.3V 54-Pin TSOP-II Tray
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC16M8A2TG-75:G

• Package: 54TSOP-II
• Density: 128 Mb
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Clock Rate: 133 MHz
• Maximum Random Access Time: 6|5.4 ns
• Operating Temperature: 0 to 70 °C

Figure 19:
Figure 20:
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM_2.fm - Rev. N 1/09 EN
WRITE Command
WRITE Burst
Notes:
A0–A9, A11: x4
COMMAND
1. BL = 2. DQM is LOW.
Data for any WRITE burst may be truncated with a subsequent WRITE command, and
data for a fixed-length WRITE burst may be immediately followed by data for a WRITE
command. The new WRITE command can be issued on any clock following the previous
WRITE command, and the data provided coincident with the new command applies to
the new command. An example is shown in Figure 21 on page 33. Data n + 1 is either the
last of a burst of two or the last desired element of a longer burst. The 128Mb SDRAM
uses a pipelined architecture and, therefore, does not require the 2n rule associated with
ADDRESS
A9, A11: x16
A0–A9: x8
A0–A8: x16
BA0, BA1
A11: x8
CLK
DQ
RAS#
CAS#
WE#
CKE
A10
CLK
CS#
WRITE
BANK,
COL n
TRANSITIONING DATA
T0
D
n
IN
HIGH
NOP
n + 1
T1
D
IN
DISABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
32
NOP
ADDRESS
COLUMN
ADDRESS
T2
BANK
DON’T CARE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DON’T CARE
T3
NOP
128Mb: x4, x8, x16 SDRAM
©1999 Micron Technology, Inc. All rights reserved.
Operations