TXC-03305AIPQ Transwitch Corporation, TXC-03305AIPQ Datasheet - Page 41

• Manufacturer Part Number: TXC-03305AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03305AIPQ

• Lead Free Status / RoHS Status: Not Compliant

INTEGRATED DJB DEVICES
The dejitter buffer (DJB) is a TranSwitch circuit design that takes in jittered DS1s from a DS3 to DS1 demux
process and smooths out the DS1s. The M13X device contains 28 of these DJBs. The option to bypass the
DJBs through a control bit, DJB, is provided when the M13X lead is low. When M13X is high, the DJBs are
unconditionally bypassed.
The DJB control bit is located at bit 7 of register 3DH. When M13X is low the DJB control bit operates as fol-
lows:
The DJBs are located in the M13X device such that when they are enabled (i.e., DJB = 1 and M13X is low), the
receive DS1 channels that are looped back are also dejittered. The XCK signal is normally used to operate the
DJBs, therefore it needs to be stable and clean. In the event that the XCK clock is lost (i.e., T3CKF = 1), the
DS3CR clock is automatically substituted in place of the XCK clock. Each DJB has an automatic self-reset
function that allows individual DJBs to be reset (i.e., only the DJBs that need to be reset are reset, while the
others operate normally) upon DJB FIFO underflow/overflow. However, when the 44.736 MHz reference clock
to the M13X is switched from XCK to DS3CR or vice versa, a manual reset via the software reset register can
be performed via software control. The following conditions activate the DJB reset:
Note that, when in loop timing mode (LPTIME = 1), the transmit clock (in this case the DS3CR signal) is used
as the 44.736 MHz reference clock for the DJBs. The DS3 reference clock frequency tolerance needs to be
within ± 20 ppm inclusive. The DS1 signals that are embedded in the demuxed DS3 signal originated at a mux
somewhere else in the system. The original frequency of these DS1s needs to be within ± 130 ppm of the nom-
inal frequency.
The M13X meets and exceeds the jitter requirements for all possible combinations of DS3 and DS1 clock off-
sets indicated below:
The M13X meets and exceeds the timing jitter requirements specified in [GR-499] for:
• DJB = 0. The DJBs are bypassed.
• DJB = 1. The DJBs are enabled and the 28 receive DS1s are dejittered.
• Software reset activated
• Hardware reset activated
• FIFO overflow or underflow (in this case, the reset is performed automatically for the individual DJB
• DS3 clock offset: +/- 20 ppm ([GR-499] Table 9-16 Line-rate accuracy parameter)
• TX DS1 clock offset: +/- 130 ppm ([GR-499] R9-64 section 9.3.2)
• RX DS1 clock offset: +/- 32 ppm ([GR-499] Table 9-13 Line-rate accuracy parameter). This parameter
• Tolerance ([GR-499] section 7.3.1)
• Transfer ([GR-499] section 7.3.2)
• Generation ([GR-499] section 7.3.3)
• Enhancement ([GR-499] section 7.3.4)
that has underflowed or overflowed)
must always be met when the line rate of the channelized DS1 signal being demultiplexed is within +/
- 32 ppm.
DATA SHEET
- 41 -
Ed. 4, September 2000
TXC-03305
TXC-03305-MB
M13X