TXC-03305AIPQ Transwitch Corporation, TXC-03305AIPQ Datasheet - Page 49

• Manufacturer Part Number: TXC-03305AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03305AIPQ

• Lead Free Status / RoHS Status: Not Compliant

INTERRUPTS
A set of interrupt request bits and corresponding mask bits is provided in the M13X. An interrupt request bit is
a bit that latches to a 1 when a certain condition occurs and can cause an interrupt to be signaled on an exter-
nal interrupt request lead (INT/IRQ) if the corresponding interrupt request mask bit is also set to a 1. An inter-
rupt request bit will remain set to a 1 even when the condition that caused it to become set is removed. An
interrupt request bit can be cleared by reading it. Two control bits, RISE and FALL, are used to control the con-
ditions for setting the non-PMDL related interrupt request bits. When RISE = 1, the interrupt request bits are
set on the entrance of an alarm/condition. When FALL = 1, the interrupt request bits are set on the exit of an
alarm/condition. When RISE and FALL are both set to 1, the interrupt request bits are set on both the entrance
and exit of an alarm/condition. When RISE and FALL are both set to 0, the interrupt request bits are disabled.
Note that the RISE and FALL bits do not affect the PMDL interrupt request bits in register 2CH. These bits are
significant only when set on the entrance of a condition and therefore only become set on the entrance of their
corresponding condition.
It is important to note that the interrupt request bits are set by their real-time counterparts, and not from other
latched bits. For example, the interrupt request bit for the R3LOS alarm is not set by the latched R3LOS bit in
register 16H but is set by the real-time R3LOS bit in register 00H.
Interrupts need to be serviced within a specific period of time after they are signaled by the INT/IRQ lead. The
table below indicates the time interval within which the interrupt request bits need to be read and processed.
Address (Hex)
Register
2A
2B
2C
25
26
27
28
29
The IRLBn and IRLBALL bits should be accessed within 131 s.
The IRLBn and IRLBDS3 bits should be accessed within 131 s.
The IRLBn bits should be accessed within 131 s.
This register should be read within 7.6 s to ensure that the IRSEF bit is read before it can
change.
This register should be read within 7.6 s to ensure that the DS3 status bits are read before
they can change.
This register should be read within 26 s to ensure that the IRDS2OOFn bits are read before
they can change.
Once a counter saturates, it must be read before the next count comes in to ensure that no
counts are lost. The worst case condition would occur for the F and M bit error counters (reg-
ister 04H in M13 format mode) and register 1BH. In this case this register and the DS3 F-bit
and M-bit counter would need to be read within 1.9 s. Since the M13X provides 16-bit wide
counters (when M13X is low) the counters do not have to be read very often to ensure that
they do not saturate. Reading the 16-bit counters in the M13X once a second is sufficient to
ensure that they will not saturate.
Once an interrupt request from one of the PMDL controllers is received it is recommended
that this register, the RX PMDL MESSAGE LENGTH register (39H), the RX PMDL FIFO
DEPTH register (3AH), and at least one byte from the RX PMDL FIFO interface register
(38H) are read within 212 s before they can be updated by the next PMDL byte.
DATA SHEET
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Description
Ed. 4, September 2000
TXC-03305
TXC-03305-MB
M13X