TXC-03305AIPQ Transwitch Corporation, TXC-03305AIPQ Datasheet - Page 77

• Manufacturer Part Number: TXC-03305AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03305AIPQ

• Lead Free Status / RoHS Status: Not Compliant

Address
1A
17
18
19
6-0
7-0
6-0
7-5
Bit
7
7
DS2OOFn
CERROR
Test Bits
Test Bits
Symbol
C3CLKI
RHIS2-
(n=7-1)
RHIS0
Latched C-bit Status/DS2 Out Of Frame Bits: The bits in this register are
the same bits listed in register location 03H, except the corresponding bit
latches on with an alarm. For example, CERROR latches to a 1 the first time
C1 is 0. A microprocessor read cycle clears all latched bits. If a DS2 OOF
remains true, the corresponding bit relatches.
TranSwitch Test Register: Used for TranSwitch testing. This register must
not be written.
C-Bit Parity C3 Clock Inhibit: A 0 enables the M13X to generate an extra
clock pulse in the CCKT clock signal for clocking the C3 bit in from external
logic. A 1 disables the generation of the C3 clock pulse. This bit must be set
to 1 if the FEAC register 1CH is used to transmit FEAC codes or if register
07H is used to send a remote loopback request via a double word FEAC
message (LBSEL = 1). If this bit is set to 0, then the FEAC messages are
derived from the external C-bit interface.
TranSwitch Test Bits: Used for TranSwitch testing. When this register is
written, the values read from these bits must be re-written.
Receive PMDL Status: The following table lists the various status indica-
tions associated with the receive PMDL message. The significance of these
bits is controlled by control bit RHIE (bit 5) in register 3DH.
These are unlatched bits that reflect the current status of the receive PMDL
processing. Codes of 101 and 110 are not defined. When a condition
occurs, all three bits are updated at once and are typically set for at least 1
byte time (i.e., 8 receive PMDL bits) after which they are reset to 0.
The priority for detecting these alarms is:
RHIS2 RHIS1 RHIS0 RHIE
0
0
0
0
0
1
1
1
1
• Abort (highest)
• Invalid Frame Received
• FCS Error Received
• Start of Message Indication
• Valid Message Received
0
0
1
1
1
0
1
0
1
DATA SHEET
0
1
0
0
1
0
1
1
0
- 77 -
X
X
X
X
X
X
X
0
1
Idle condition
Start of message indication
Valid message received; (FCS checked OK), or the
receive FIFO needs servicing (full or overflow).
Valid message received; (FCS checked OK), or the
receive FIFO needs servicing (half full or more).
Message received with FCS error
Abort message received
Invalid Frame received. (i.e., a frame with a non-
integral number of bytes or with a number of bytes
(after destuffing) less than 5).
Unused Code. See note below.
Unused code. (Make sure that bit-oriented codes,
do not cause these bits to become set). This com-
bination of bit settings should never appear.
Description
Condition Present
Ed. 4, September 2000
TXC-03305
TXC-03305-MB
M13X