TXC-03305AIPQ Transwitch Corporation, TXC-03305AIPQ Datasheet - Page 85

• Manufacturer Part Number: TXC-03305AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03305AIPQ

• Lead Free Status / RoHS Status: Not Compliant

Address
24
25
26
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
AISCEQ0
AISXEQ1
Reserved
IRLBDS3
IRLBALL
Symbol
IRLB25
IRLB21
IRLB17
IRLB13
IRLB26
IRLB22
IRLB18
IRLB14
IRLB10
Test Bit
Test Bit
Test Bit
Test Bit
IRLB9
IRLB5
IRLB1
IRLB6
IRLB2
SEF
DS3 AIS Detection: This bit provides a filtered indication of the receive
DS3 X-bits being equal to 1. Two counters are used to implement this filter,
a mod 16 counter CXE1 which counts the receive DS3 X-bit pairs = 11, and
a mod 4 counter CXE0 which counts the receive DS3 X-bit pairs = 00.
When either counter matures, both counters are reset. The AISXEQ1 bit
becomes latched when the CXE1 counter matures. This bit is used for
determining if the X-bits = 1 condition is met when R3AIS2 = 0, R3AIS1 =
0, and R3AIS0 = 1 in register 21H (ANSI DS3 defined AIS detection). This
is a latched bit, and clears when it is read by the microprocessor. This bit
will relatch if the condition that causes this bit to latch is still present.
DS3 AIS Detection: This bit provides a filtered indication of the receive
DS3 C-bits equal to 0. This bit will be set if the M13X receives 7 contiguous
DS3 frames with 30 or fewer DS3 C-bits set to 1. This bit is used for deter-
mining if the C Bits = 0 condition is met when R3AIS2 = 0, R3AIS1 = 0, and
R3AIS0 = X, where X means don’t care. This is a latched bit, and clears
when it is read by the microprocessor. This bit will relatch if the condition
that causes this bit to latch is still present.
Test Bit: Used for diagnostic purposes. This bit must always be ignored.
Test Bit: Used for diagnostic purposes. This bit must always be ignored.
Test Bit: Used for diagnostic purposes. This bit must always be ignored.
Test Bit: Used for diagnostic purposes. This bit must always be ignored.
Reserved: This bit must always be ignored.
Severely Errored Frame Indication: A 1 indicates a Severely Errored
Frame (SEF) has been detected. A SEF is defined as 3 out of 16 F-bits are
in error, utilizing a sliding window of 16 F-bits. This is a latched bit, and
clears when it is read by the microprocessor. This bit will relatch if the con-
dition that causes it to latch is still present.
Receive Loopback Interrupt Requests: The bits in these registers are
interrupt request bits for the corresponding remote loopback request bits in
register 08H. The RISE and FALL bits in register 3FH control whether these
interrupt request bits are set on the entrance or exit of an alarm condition,
or both. If the corresponding interrupt request mask bit is set to a 1 in regis-
ter 2EH then the INT/IRQ lead goes active to signal an interrupt request to
the external microprocessor when a bit in these registers becomes set to 1.
A microprocessor read cycle clears all set interrupt request bits in the regis-
ter that is read.
Receive Loopback Interrupt Requests: The bits in these registers are
interrupt request bits for the corresponding remote loopback request bits in
register 09H. The RISE and FALL bits in register 3FH control whether these
interrupt request bits are set on the entrance or exit of an alarm condition,
or both. If the corresponding interrupt request mask bit is set to a 1 in regis-
ter 2FH then the INT/IRQ lead goes active to signal an interrupt request to
the external microprocessor when a bit in these registers becomes set to 1.
A microprocessor read cycle clears all set interrupt request bits in the regis-
ter that is read.
DATA SHEET
- 85 -
Description
Ed. 4, September 2000
TXC-03305
TXC-03305-MB
M13X