WJLXT971ALE.A4-857346 Cortina Systems Inc, WJLXT971ALE.A4-857346 Datasheet - Page 30

• Manufacturer Part Number: WJLXT971ALE.A4-857346
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT971ALE.A4-857346

• Lead Free Status / RoHS Status: Compliant

LXT971A PHY
Datasheet
249414, Revision 5.2
13 September 2007
Notes:
5.3.2
5.3.2.1
5.3.2.2
5.4
Cortina Systems
The digital and analog circuits require 3.3 V supplies (VCCA and VCCD). These inputs
may be supplied from a single source. Each supply input must be de-coupled to ground.
An additional supply may be used for the MII (VCCIO). The supply may be either 2.5 V or
3.3 V. Also, the inputs on the MII interface are tolerant to 5 V signals from the controller on
the other side of the MII interface. For MII I/O characteristics, see
Characteristics
Clock Requirements
External Crystal/Oscillator
The LXT971A PHY requires a reference clock input that is used to generate transmit
signals and recover receive signals. It may be provided by either of two methods: by
connecting a crystal across the oscillator pins (XI and XO) with load capacitors, or by
connecting an external clock source to pin XI.
The connection of a clock source to the XI pin requires the XO pin to be left open. To
minimize transmit jitter, Cortina recommends a crystal-based clock instead of a derived
clock (that is, a PLL-based clock).
A crystal is typically used in NIC applications. An external 25 MHz clock source, rather
than a crystal, is frequently used in switch applications. For clock timing requirements, see
Table 25, I/O Characteristics - REFCLK/XI and XO Pins, on page
MDIO Clock
The MII management channel (MDIO) also requires an external clock. The managed data
clock (MDC) speed is a maximum of 8 MHz.
Initialization
This section includes the following topics:
When the LXT971A PHY is first powered on, reset, or encounters a link failure state, it
checks the MDIO register configuration bits to determine the line speed and operating
conditions to use for the network link.
Table 13
set by the Hardware Control or MDIO interface.
®
1. Bring up power supplies as close to the same time as possible.
2. As a matter of good practice, keep power supplies as clean as possible.
• VCCIO
•
•
•
•
LXT971A Single-Port 10/100 Mbps PHY Transceiver
Section 5.4.1, MDIO Control Mode and Hardware Control Mode
Section 5.4.2, Reduced-Power Modes
Section 5.4.3, Reset
Section 5.4.4, Hardware Configuration Settings
shows the LXT971A PHY initialization sequence. The configuration bits may be
1
- MII Pins, on page
62.
63.
Table 24, Digital I/O
5.4 Initialization
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