WJLXT971ALE.A4-857346 Cortina Systems Inc, WJLXT971ALE.A4-857346 Datasheet - Page 32

• Manufacturer Part Number: WJLXT971ALE.A4-857346
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT971ALE.A4-857346

• Lead Free Status / RoHS Status: Compliant

LXT971A PHY
Datasheet
249414, Revision 5.2
13 September 2007
5.4.2
5.4.2.1
5.4.2.2
5.4.2.3
Note:
Cortina Systems
In the Hardware Control Mode, the LXT971A PHY disables direct-write operations to the
MDIO registers through the MDIO Interface.
On power-up or hardware reset, the LXT971A PHY reads the Hardware Control Interface
pins and sets the MDIO registers accordingly.
When the network link is forced to a specific configuration, the LXT971A PHY immediately
begins operating the network interface as commanded. When auto-negotiation is enabled,
the LXT971A PHY begins the auto-negotiation/parallel-detection operation.
Reduced-Power Modes
This section discusses the LXT971A PHY reduced-power modes.
Hardware Power Down
The hardware power-down mode is controlled by the PWRDWN pin. When PWRDWN is
High, the following conditions are true:
Software Power Down
Software power-down control is provided by register bit 0.11 in the Control Register.
During soft power-down, the following conditions are true:
Sleep Mode
The LXT971A PHY supports a power-saving sleep mode. Sleep mode is enabled when
SLEEP is asserted via pin 32(LQFP)/H7(PBGA). The value of pin 32/H7 can be
overridden by register bit 16.6 in managed mode as listed in
Register - Address 16, Hex 10, on page
when SLEEP is enabled and no energy is detected on the twisted-pair input for 1 to 3
seconds. (The time is controlled by register bits 16.4:3 in the Configuration Register, with
a default of 3.04 seconds.)
During this mode, the LXT971A PHY still responds to management transactions (MDC/
MDIO). In this mode the power consumption is minimized, and the supply current is
reduced below the maximum value. If the LXT971A PHY detects activity on the twisted-
pair inputs, it comes out of the sleep state and checks for link. If no link is detected in from
1 to 3 seconds (the time is programmable) it reverts to the low power sleep state.
Sleep mode is not functional in fiber network applications.
®
• Allow auto-negotiation/parallel-detection
• The LXT971A PHY network port and clock are shut down.
• All outputs are tristated.
• All weak pad pull-up and pull-down resistors are disabled.
• The MDIO registers are not accessible.
• The network port is shut down.
• The MDIO registers remain accessible.
LXT971A Single-Port 10/100 Mbps PHY Transceiver
— 10BASE-T, Half-Duplex
86. The LXT971A PHY enters into sleep mode
Table 56, Configuration
5.4 Initialization
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