FLLXT971ABC.A4 Intel, FLLXT971ABC.A4 Datasheet - Page 44

• Manufacturer Part Number: FLLXT971ABC.A4
• Manufacturer: Intel

Specifications of FLLXT971ABC.A4

• Lead Free Status / RoHS Status: Not Compliant

Intel
5.6.4
5.6.5
5.6.6
44
Table 13. Carrier Sense, Loopback, and Collision Conditions
®
LXT971A Single-Port 10/100 Mbps PHY Transceiver
Carrier Sense
Carrier Sense (CRS) is an asynchronous output.
Table 13
signals. Carrier sense is not generated when a packet is transmitted and in full-duplex mode.
Error Signals
When the LXT971A Transceiver is in 100 Mbps mode and receives an invalid symbol from the
network, it asserts RX_ER and drives “0101” on the RXD pins.
When the MAC asserts TX_ER, the LXT971A Transceiver drives “H” symbols out on the TPFOP/
N pins.
Collision
The LXT971A Transceiver asserts its collision signal asynchronously to any clock whenever the
line state is half-duplex and the transmitter and receiver are active at the same time.
summarizes the conditions for assertion of carrier sense, data loopback, and collision signals.
100
Mbps
10
Mbps
Speed
•
•
1. Test Loopback is enabled when Register bit 0.14 = 1.
2. For descriptions of Test Loopback and Operational Loopback, see
CRS is always generated when the LXT971A Transceiver receives a packet from the line.
CRS is also generated when the LXT971A Transceiver is in half-duplex mode when a packet
is transmitted.
summarizes the conditions for assertion of carrier sense, data loopback, and collision
Full-Duplex
Half-Duplex
Full-Duplex
Half-Duplex,
Register bit 16.8 = 0
Half-Duplex,
Register bit 16.8 = 1
Duplex Condition
Receive Only
Transmit or Receive
Receive Only
Transmit or Receive
Transmit or Receive
Carrier Sense
Loop-
back
Test
Yes
Yes
Yes
No
No
1, 2
Section 5.6.7, “Loopback” on page
Operational
back
Loop-
Yes
No
No
No
No
1, 2
Document Number: 249414-003
Revision Date: June 18, 2004
None
Transmit and Receive
None
Transmit and Receive
Transmit and Receive
Collision
Table 13
Datasheet
45.