FLLXT971ABC.A4 Intel, FLLXT971ABC.A4 Datasheet - Page 66

• Manufacturer Part Number: FLLXT971ABC.A4
• Manufacturer: Intel

Specifications of FLLXT971ABC.A4

• Lead Free Status / RoHS Status: Not Compliant

Intel
6.3
66
®
LXT971A Single-Port 10/100 Mbps PHY Transceiver
Fiber Interface
The fiber interface consists of an LVPECL transmit and receive pair to an external fiber-optic
transceiver. Both 3.3 V fiber-optic transceivers and 5 V fiber-optic transceivers can be used with
the LXT971A Transceiver. For details on fiber interface designs and recommendations for Intel
PHYs, see the document on 100BASE-FX fiber optics listed in
As shown in
•
•
•
•
The transmit pair should be DC-coupled with the 50 Ω/16 Ω pull-up combination.
The transmit pair should have a 2.74 kΩ pull-down resistor to prevent PHY-to-fiber
transceiver crosstalk amplification in power-down, loopback, and reset states. (See the fiber
interface application note.)
The receive pair should be DC-coupled with an emitter current path for the fiber transceiver.
The signal detect pin should be DC-coupled with an emitter current path for the fiber
transceiver.
Figure
25, the following should occur in 3.3 V fiber transceiver applications:
Chapter 1.0, “Related
Document Number: 249414-003
Revision Date: June 18, 2004
Documents”.
Datasheet