PIC16LF1847T-I/SO Microchip Technology, PIC16LF1847T-I/SO Datasheet - Page 249

• Manufacturer Part Number: PIC16LF1847T-I/SO
• Description: 14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core, Nan
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ mTouch™ 16Fr

Specifications of PIC16LF1847T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-SOIC (0.295", 7.50mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

25.5.2 SLAVE RECEPTION
When the R/W bit of a matching received address byte
is clear, the R/W bit of the SSPxSTAT register is
cleared. The received address is loaded into the
SSPxBUF register and acknowledged.
When the overflow condition exists for a received
address, then not Acknowledge is given. An overflow
condition is defined as either bit BF of the SSPxSTAT
register is set, or bit SSPOV of the SSPxCON1 register
is set. The BOEN bit of the SSPxCON3 register modi-
fies this operation. For more information see
Register
An MSSPx interrupt is generated for each transferred
data byte. Flag bit, SSPxIF, must be cleared by soft-
ware.
When the SEN bit of the SSPxCON2 register is set,
SCLx will be held low (clock stretch) following each
received byte. The clock must be released by setting
the CKP bit of the SSPxCON1 register, except
sometimes in 10-bit mode. See
Master Mode”
25.5.2.1 7-bit Addressing Reception
This section describes a standard sequence of events
for the MSSPx module configured as an I
7-bit Addressing mode. All decisions made by hard-
ware or software and their effect on reception.
Figure 25-13
reference for this description.
This is a step by step process of what typically must
be done to accomplish I
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Software clears SSPxIF.
11. Software
12. Steps 8-12 are repeated for all received bytes
13. Master sends Stop condition, setting P bit of
 2011 Microchip Technology Inc.
Start bit detected.
S bit of SSPxSTAT is set; SSPxIF is set if inter-
rupt on Start detect is enabled.
Matching address with R/W bit clear is received.
The slave pulls SDAx low sending an ACK to the
master, and sets SSPxIF bit.
Software clears the SSPxIF bit.
Software
SSPxBUF clearing the BF flag.
If SEN = 1; Slave software sets CKP bit to
release the SCLx line.
The master clocks out a data byte.
Slave drives SDAx low sending an ACK to the
master, and sets SSPxIF bit.
SSPxBUF clearing BF.
from the Master.
SSPxSTAT, and the bus goes Idle.
25-4.
and
for more detail.
reads
reads
Figure 25-14
2
the
C communication.
received
received
is used as a visual
Section 25.2.3 “SPI
address
byte
2
C Slave in
from
from
Preliminary
25.5.2.2 7-bit Reception with AHEN and DHEN
Slave device reception with AHEN and DHEN set
operate the same as without these options with extra
interrupts and clock stretching added after the 8th fall-
ing edge of SCLx. These additional interrupts allow the
slave software to decide whether it wants to ACK the
receive address or data byte, rather than the hard-
ware. This functionality adds support for PMBus™ that
was not present on previous versions of this module.
This list describes the steps that need to be taken by
slave software to use these options for I
cation.
address and data holding.
operation with the SEN bit of the SSPxCON2 register
set.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Slave clears SSPxIF.
11. SSPxIF set and CKP cleared after 8th falling
12. Slave looks at ACKTIM bit of SSPxCON3 to
13. Slave reads the received data from SSPxBUF
14. Steps 7-14 are the same for each received data
15. Communication is ended by either the slave
Note: SSPxIF is still set after the 9th falling edge of
S bit of SSPxSTAT is set; SSPxIF is set if inter-
rupt on Start detect is enabled.
Matching address with R/W bit clear is clocked
in. SSPxIF is set and CKP cleared after the 8th
falling edge of SCLx.
Slave clears the SSPxIF.
Slave can look at the ACKTIM bit of the
SSPxCON3 register to determine if the SSPxIF
was after or before the ACK.
Slave reads the address value from SSPxBUF,
clearing the BF flag.
Slave sets ACK value clocked out to the master
by setting ACKDT.
Slave releases the clock by setting CKP.
SSPxIF is set after an ACK, not after a NACK.
If SEN = 1 the slave hardware will stretch the
clock after the ACK.
edge of SCLx for a received data byte.
determine the source of the interrupt.
clearing BF.
byte.
sending an ACK = 1, or the master sending a
Stop condition. If a Stop is sent and Interrupt on
Stop Detect is disabled, the slave will only know
by polling the P bit of the SSTSTAT register.
Figure 25-15
SCLx even if there is no clock stretching and
BF has been cleared. Only if NACK is sent
to Master is SSPxIF not set
PIC16(L)F1847
displays a module using both
Figure 25-16
DS41453B-page 249
2
includes the
C communi-