PIC18F65K90T-I/PT Microchip Technology, PIC18F65K90T-I/PT Datasheet - Page 122

• Manufacturer Part Number: PIC18F65K90T-I/PT
• Description: 32kB Flash, 2kB RAM, 1kB EE, NanoWatt XLP, LCD 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F65K90T-I/PT

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Timers: 8
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Lead Free Status / Rohs Status: Details

PIC18F87K90 FAMILY
REGISTER 8-1:
DS39957D-page 122
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
EEPGD
R/W-x
When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error
condition.
EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access Flash program memory
0 = Access data EEPROM memory
CFGS: Flash Program/Data EEPROM or Configuration Select bit
1 = Access Configuration registers
0 = Access Flash program or data EEPROM memory
Unimplemented: Read as ‘0’
FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by the TBLPTR on the next WR command
0 = Perform write-only
WRERR: Flash Program/Data EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal
0 = The write operation completed
WREN: Flash Program/Data EEPROM Write Enable bit
1 = Allows write cycles to Flash program/data EEPROM
0 = Inhibits write cycles to Flash program/data EEPROM
WR: Write-Control bit
1 = Initiates a data EEPROM erase/write cycle, or a program memory erase cycle or write cycle
0 = Write cycle to the EEPROM is complete
RD: Read Control bit
1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only
0 = Does not initiate an EEPROM read
R/W-x
CFGS
(cleared by completion of an erase operation)
operation or an improper write attempt)
(The operation is self-timed and the bit is cleared by hardware once the write is complete. The
WR bit can only be set (not cleared) in software.)
be set (not cleared) in software. The RD bit cannot be set when EEPGD = 1 or CFGS = 1.)
EECON1: DATA EEPROM CONTROL REGISTER 1
S = Settable bit
W = Writable bit
‘1’ = Bit is set
U-0
—
R/W-0
FREE
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
WRERR
R/W-x
(1)
(1)
WREN
R/W-0
 2009-2011 Microchip Technology Inc.
x = Bit is unknown
R/S-0
WR
R/S-0
RD
bit 0