PIC18F65K90T-I/PT Microchip Technology, PIC18F65K90T-I/PT Datasheet - Page 170

• Manufacturer Part Number: PIC18F65K90T-I/PT
• Description: 32kB Flash, 2kB RAM, 1kB EE, NanoWatt XLP, LCD 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F65K90T-I/PT

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Timers: 8
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Lead Free Status / Rohs Status: Details

PIC18F87K90 FAMILY
TABLE 11-10: PORTE FUNCTIONS
DS39957D-page 170
RE0/LCDBIAS1/
P2D
RE1/LCDBIAS2/
P2C
RE2/LCDBIAS3/
P2B
RE3/COM0/
P3C/CCP9/
REFO
RE4/COM1/
P3B/CCP8
RE5/COM2/
P1C/CCP7
RE6/COM3/
P1B/CCP6
Legend:
Note 1:
Pin Name
2:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared.
This bit is unimplemented in PIC18FX5K90 devices.
LCDBIAS1
LCDBIAS2
LCDBIAS3
Function
CCP9
COM0
REFO
COM1
COM2
COM3
CCP8
CCP7
CCP6
RE0
P2D
RE1
P2C
RE2
P2B
RE3
P3C
RE4
P3B
RE5
P1C
RE6
P1B
(2)
Setting
TRIS
—
—
0
1
0
0
1
0
0
1
x
0
0
1
x
0
0
1
x
0
1
x
0
0
1
0
1
x
0
0
1
0
1
x
0
0
1
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
ANA
ANA
ANA
ANA
ANA
ANA
ANA
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
—
—
—
—
—
—
—
LATE<0> data output.
PORTE<0> data input.
LCD module bias voltage input.
ECCP2 PWM Output D. May be configured for tri-state during
Enhanced PWM shutdown events.
LATE<1> data output.
PORTE<1> data input.
LCD module bias voltage input.
ECCP2 PWM Output C.
May be configured for tri-state during Enhanced PWM shutdown events.
LATE<2> data output.
PORTE<2> data input.
LCD module bias voltage input.
ECCP2 PWM Output B. May be configured for tri-state during
Enhanced PWM shutdown events.
LATE<3> data output.
PORTE<3> data input.
LCD Common 0 output; disables all other outputs.
ECCP3 PWM Output C. May be configured for tri-state during
Enhanced PWM shutdown events.
CCP9 compare/PWM output; takes priority over port data.
CCP9 capture input.
Reference output clock.
LATE<4> data output.
PORTE<4> data input.
LCD Common 1 output; disables all other outputs.
ECCP3 PWM Output B. May be configured for tri-state during
Enhanced PWM shutdown events.
CCP8 Compare/PWM output; takes priority over port data.
CCP8 capture input.
LATE<5> data output.
PORTE<5> data input.
LCD Common 2 output; disables all other outputs.
ECCP1 PWM Output C. May be configured for tri-state during
Enhanced PWM shutdown events.
CCP7 Compare/PWM output; takes priority over port data.
CCP7 capture input.
LATE<6> data output.
PORTE<6> data input.
LCD Common 3 output; disables all other outputs.
ECCP1 PWM Output B. May be configured for tri-state during
Enhanced PWM shutdown events.
CCP6 Compare/PWM output; takes priority over port data.
CCP6 capture input.
Description
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