PIC24FV32KA302-E/SP Microchip Technology, PIC24FV32KA302-E/SP Datasheet - Page 51

• Manufacturer Part Number: PIC24FV32KA302-E/SP
• Description: 32KB Flash, 2KB RAM, 512B EEPROM, 16 MIPS, 12-bit ADC, CTMU, 5V 28 SPDIP .300in
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FV32KA302-E/SP

• Processor Series: PIC24FV
• Core: PIC
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• Package / Case: SPDIP-28
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 23
• Eeprom Size: 512 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Lead Free Status / Rohs Status: Details

TABLE 4-21:
TABLE 4-22:
TABLE 4-23:
CRCCON1
CRCCON2
CRCXORL
CRCXORH
CRCDATL
CRCDATH
CRCWDATL
CRCWDATH
Legend:
RCON
OSCCON
CLKDIV
OSCTUN
REFOCON
HLVDCON
Legend:
Note 1:
DSCON
DSWAKE
DSGPR0
DSGPR1
Legend:
Note 1:
File Name
File Name
Name
File
2:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
RCON register Reset values are dependent on type of Reset.
OSCCON register Reset values are dependent on configuration fuses and by type of Reset.
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
The Deep Sleep registers DSGPR0 and DSGPR1 are only reset on a V
Addr
0758
075A
075C
075E
074E
Addr
0740
0742
0744
0748
0756
Addr
0640
0642
0644
0646
0648
064A
064C
064E
Bit 15
DSEN
CRC REGISTER MAP
CLOCK CONTROL REGISTER MAP
DEEP SLEEP REGISTER MAP
HLVDEN
TRAPR
—
ROEN
Bit 15
ROI
—
—
CRCEN
Bit 15
X15
X31
—
Bit 14
—
—
IOPUWR SBOREN
COSC2
DOZE2
Bit 14
—
—
—
Bit 14
Bit 13
X14
X30
—
—
—
—
ROSSLP
COSC1
HLSIDL
DOZE1
Bit 13
—
Bit 12
CSIDL
Bit 13
—
—
X13
X29
—
COSC0
DOZE0
ROSEL
LVREN
Bit 12
—
—
VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT CRCISEL CRCGO LENDIAN
DWIDTH4 DWIDTH3 DWIDTH2 DWIDTH1 DWIDTH0
Bit 11
Bit 12
—
—
X12
X28
RODIV3 RODIV2 RODIV1 RODIV0
DOZEN
Bit 11
—
—
—
—
Bit 10
—
—
Bit 11
X27
X11
RCDIV2 RCDIV1 RCDIV0
DPSLP
NOSC2 NOSC1
Bit 10
—
—
DD
Bit 9
—
—
Bit 10
X10
X26
POR event.
Bit 9
CM
—
—
RTCCWDIS
DSINT0
Bit 8
Bit 9
X25
X9
NOSC0 CLKLOCK
PMSLP
Bit 8
—
—
DSGPR0
DSGPR1
CRCWDATH
CRCWDATL
DSFLT
CRCDATH
CRCDATL
Bit 8
X24
Bit 7
X8
—
EXTR
VDIR
Bit 7
—
—
—
Bit 7
X23
X7
—
Bit 6
—
—
BGVST
SWR
Bit 6
—
—
—
—
Bit 6
X22
Bit 5
X6
—
SWDTEN
—
—
IRVST
LOCK
TUN5
Bit 5
—
—
DSWDT DSRTCC
Bit 5
Bit 4
X21
—
X5
WDTO
TUN4
Bit 4
—
—
—
—
PLEN4
Bit 3
Bit 4
X20
—
X4
HLVDL3
SLEEP
TUN3
Bit 3
CF
—
—
ULPWDIS
DSMCLR
PLEN3
Bit 3
X19
Bit 2
X3
SOSCDRV SOSCEN
HLVDL2
TUN2
Bit 2
IDLE
—
—
PLEN2
Bit 2
X18
X2
—
DSBOR
Bit 1
HLVDL1
—
TUN1
BOR
Bit 1
PLEN1
—
—
Bit 1
X17
X1
—
RELEASE
DSPOR
OSWEN (Note 2)
HLVDL0
Bit 0
PLEN0
TUN0
POR
Bit 0
Bit 0
X16
—
—
—
—
Resets
(Note 1)
Resets
Resets
0000
0000
0000
0000
0000
0000
0000
0000
xxxx
xxxx
xxxx
xxxx
3140
0000
0000
0000
All
All
All
(1)