TDA9955HL/17/C1:55 NXP Semiconductors, TDA9955HL/17/C1:55 Datasheet - Page 36

• Manufacturer Part Number: TDA9955HL/17/C1:55
• Description: TDA9955HL/LQFP100/TRAYBDP//17/
• Manufacturer: NXP Semiconductors
• Type: Videor

Specifications of TDA9955HL/17/C1:55

• Resolution (bits): 8 b
• Sampling Rate (per Second): 170M
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 1.75 V ~ 1.85 V, 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935281545551; TDA9955HL/17/C1-S; TDA9955HL/17/C1-S

NXP Semiconductors
TDA9955HL_1
Product data sheet
9.2.15 Sync output selection registers
9.2.16 Output polarity control register
Table 45.
Legend: * = default value
Table 46.
Legend: * = default value
Bit
7 to 5
4 to 3
2 to 0
Bit
7 to 6 -
5
4
3
2
Symbol
CS_POL
HS_POL
VS_POL
FREF_POL W
Symbol
CS_SEL[2:0] W
VS_SEL[1:0] W
HS_SEL[2:0] W
CSVSHS_SEL register (address E8h) bit description
POL_CTRL register (address E9h) bit description
Access Value Description
W
W
W
W
Access Value Description
Rev. 01 — 17 March 2008
0*
1
0*
1
0*
1
0*
1
000*
001
xxx
00*
01
10
11
000*
001
010
011
100
101
110
111
Triple 8-bit analog-to-digital video converter for HDTV
not used
composite sync polarity: pin CS; composite sync signal
horizontal sync polarity: pin HS; horizontal sync signal
vertical sync polarity: pin VS; vertical sync signal
field reference polarity: pin FREF; field reference signal
does not toggle; positive signal
toggles; negative signal
does not toggle; positive signal
toggles; negative signal
does not toggle; positive signal
toggles; negative signal
does not toggle; positive signal
toggles; negative signal
composite sync selection: selects the signal outputs
on pin CS
vertical sync selection: selects the signal outputs on
pin VS
horizontal sync selection: selects the signal outputs on
HS pin
composite signal from the SDRS
combination of HS and VS
for test
vertical sync from the SDRS
vertical sync from the VHREF timing generator
undefined
undefined
horizontal sync from the PLL output
for test
horizontal sync from the SDRS
horizontal sync from the HDMI receiver
HS signal generated by the VHREF timing generator
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undefined
undefined
TDA9955HL
© NXP B.V. 2008. All rights reserved.
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