XR88C681CP/40 Exar Corporation, XR88C681CP/40 Datasheet - Page 20

• Manufacturer Part Number: XR88C681CP/40
• Description: Dual Channel UART
• Manufacturer: Exar Corporation

Specifications of XR88C681CP/40

• Features: *
• Number Of Channels: 2, DUART
• Fifo's: 1 Byte, 3 Byte
• Voltage - Supply: 5V
• With Parallel Port: Yes
• With Cmos: Yes
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2. Write a logic “1” to IMR[7].
ISR[6] Delta Break Indicator - Channel B
When this bit is set, it indicates that the Channel B
receiver has detected the beginning or end of a received
break (RB). This bit is cleared (or reset) when the CPU
invokes a channel B “RESET BREAK CHANGE
INTERRUPT” command (see Table 3).
information into the DUART’s response to a BREAK
condition, please see Section G.2.
ISR[5] RXRDY/FFULL B - Channel B Receiver Ready
or FIFO Full
The function of this bit is selected by programming
MR1B[6].
indicator (RXRDYB), it indicates that at least one
character of data is in RHRB and is ready to be read by the
CPU. This bit is set when a character is transferred from
the receiver shift register to RHRB and is cleared when
the CPU reads the RHRB.
characters in RHRB after the read operation, the bit will be
set again after RHRB is “popped”.
If this bit is programmed as FIFO full indicator (FFULLB),
it is set when a character is transferred from the RSR to
RHRB and the transfer causes RHRB to become full. This
bit is cleared when the CPU reads RHRB; and thereby
“popping” the FIFO, making room for the next character. If
a character is waiting in the RSR because RHRB is full,
this bit will be set again after the read operation, when that
character is loaded into RHRB.
Note:
ISR[4] TXRDYB - Channel B Transmitter Ready
This bit is a duplicate of TXRDY B, SRB[2].
This bit, when set, indicates that THRB is empty and is
ready to accept a character from the CPU. The bit is
cleared when the CPU writes a new character to THRB;
and is set again, when that character is transferred to the
TSR. TXRDYB is set when the transmitter is initially
enabled and is cleared when the transmitter is disabled.
If this bit is configured to reflect the FFULLB indicator, this
bit will not be set (nor will produce an interrupt request) if
one or two characters are still remaining in RHRB, following
data reception. Hence, it is possible that the last two char-
acters in a string of data (being received) could be lost due
to this phenomenon.
Rev. 2.11
If programmed as the Receiver Ready
If there are still more
For more
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Characters loaded into THRB while the transmitter is
disabled will not be transmitted.
ISR[3] Counter Ready
In the TIMER mode, the C/T (Counter/Timer) will set
ISR[3] once each cycle of the resultant square wave
(available at the OP3 pin). ISR[3] will be cleared by
invoking the “STOP COUNTER” command. Bear in mind,
that in the TIMER mode, the “STOP COUNTER”
command will not stop the C/T.
In the COUNTER mode, this bit is set when the counter
reaches the terminal count (0000
the counter is stopped by a “STOP COUNTER”
command. When the Counter/Timer is in the COUNTER
Mode, the “STOP COUNTER” command will stop the
Counter/Timer.
ISR[2]: Delta Break A - Channel A Change in Break
Assertion of this bit indicates that the channel A receiver
has detected the beginning of or the end of a received
break (RB). This bit is cleared when the CPU invokes a
channel A “RESET BREAK CHANGE INTERRUPT”
command.
response to a BREAK condition, please see Section G.2.
ISR[1] RXRDYA/FFULL A - Channel A Receiver
Ready or FIFO Full
The function of this bit is selected by programming
MR1A[6].
indicator (RXRDYA), this bit indicates that there is at least
one character of data in RHRA, and is ready to be read by
the CPU. This bit is set when a character is transferred
from the RSR to RHRA and is cleared when the CPU
reads (or “pops”) RHRA. If there are still more characters
in RHRA, following the read operation, the bit will be set
again after RHRA is “popped”.
If this bit is programmed as the FIFO (RHR) full indicator
(FFULLA), it is set when a character is transferred from
the RSR to RHRA and the newly transferred character
causes RHRA to become full. This bit is cleared when the
CPU reads RHRA. If a character is waiting in the RSR
because RHRA is full, this bit will be set again, following
the read operation, when that character is loaded into
RHRA.
Note:
If this bit is configured to reflect the FFULLA indicator, this
bit will not be set (nor will produce an interrupt request) if
If programmed as the Receiver Ready
For more information into the DUART’s
16
) and is cleared when