XR88C681CP/40 Exar Corporation, XR88C681CP/40 Datasheet - Page 23

• Manufacturer Part Number: XR88C681CP/40
• Description: Dual Channel UART
• Manufacturer: Exar Corporation

Specifications of XR88C681CP/40

• Features: *
• Number Of Channels: 2, DUART
• Fifo's: 1 Byte, 3 Byte
• Voltage - Supply: 5V
• With Parallel Port: Yes
• With Cmos: Yes
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

program control to a specific location in system memory.
For CPUs that employ direct interrupts, this “location” is
fixed by the CPU circuitry itself.
For Example:
If the
asserted, the CPU will branch program control to location
0003
design of the 8051 P) and cannot be changed by the
user.
(External) Vectored Interrupt Processing
CPUs that employ this form of interrupt processing
typically have an Interrupt Acknowledge output pin. This
“IACK” or “
vector” information onto the Data Bus, via external
(non-DUART) hardware. The term “External” is used to
describe this form of vectored-interrupt processing;
The information presented in Table 7 is discussed in detail in the following sections.
(Interrupt Mode 0)
Rev. 2.11
16
-
INT0 interrupt request input pin, of the 8051 C, is
in system memory. This location is fixed (by circuit
68HC11 C
8080A P
8051 C
Z-80 P
8085 P
Z-80 P
P/ C
-
INTA” output will be used to gate “interrupt
Table 7. Summary of P/ C and their types of Interrupt Processing (I - Mode)
Type of Interrupt Processing
Direct and External Vectored
External Vectored
External Vectored
Direct Interrupt
Direct
Direct
23
The 8051 C has two external Interrupt Request inputs:
and
The 8080A P will allow the use of up to 8 different op codes
for
The 8080A CPU module will output an interrupt ac-
knowledge output,
the “CALL” instructions on to the Data Bus.
The 8085 P has three “Direct” external Interrupt Request
inputs: RST 7.5, RST 6.5, and RST 5.5. Additionally, this P
has the exact same “vector” options as does the 8080A P.
The 68HC11 C has a single “maskable” external Interrupt
Request input;
The Z-80 CPU uses the exact same approach as presented
for the 8080A CPU.
The Z-80 will branch to 0038H in system memory if the
interrupt request pin is asserted.
because the location of the interrupt service routine is
determined by hardware “external” to the DUART. For
some CPUs, (such as the 8080A and the 8085 P), this
“interrupt vector” information is a one byte op-code for a
CALL instruction to a special “RESTART subroutine”.
The location of this “RESTART subroutine” is fixed by
CPU circuit design. If the user employs this approach for
interrupt processing, he/she is responsible for insuring
that either the interrupt service routine, or an
unconditional branch instruction (to the interrupt service
routine) resides at this location in memory.
Each of these Interrupt Processing techniques will be
presented in greater detail in the following sections.
As mentioned earlier, the DUART should be operating in
the I-Mode, when interfaced to the P/ C presented in
Table 7.
processing that is employed by each of these Ps/ Cs.
“CALL” instructions to the Interrupt Service Routines.
-
INT1.
Table 7 also presents the type of interrupt
-
IRQ.
-
INTA, which can be used to “gate”
Comments
XR88C681
-
-
INT
INT0