XR88C681CP/40 Exar Corporation, XR88C681CP/40 Datasheet - Page 47

• Manufacturer Part Number: XR88C681CP/40
• Description: Dual Channel UART
• Manufacturer: Exar Corporation

Specifications of XR88C681CP/40

• Features: *
• Number Of Channels: 2, DUART
• Fifo's: 1 Byte, 3 Byte
• Voltage - Supply: 5V
• With Parallel Port: Yes
• With Cmos: Yes
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(e.g., AD0 - AD15 becomes D0 - D15, A16/S3 - A19/S6
becomes S3 - S6). A second group of multiplexed pins is
controlled by the MN/
the “min” mode is selected and pins 24 through 31 take on
the control definitions shown under the MN/
When MN/
mode.
applications in which the 8086 P requires support from
the 8087 numeric data processor (NDP). In this mode, a
special bus controller (the 8288) is required to generate
the memory and I/O control bus signals.
The 8086 P contains two interrupt request inputs: INTR
and NMI. NMI is the active-high “non-maskable” interrupt
-
S2
0
0
0
0
1
1
1
1
Rev. 2.11
Table 15. 8086 Processor State/8288 Bus Controller Active Output as a function of
This mode is intended for more complex
-
MX is low, the 8086 P is operating in the “max”
-
S1
0
0
1
1
0
0
1
1
Pin Number
24
25
26
27
28
29
30
31
Table 14. MN/
-
-
MX input pin. When this pin is high,
S0
0
1
0
1
0
1
0
1
-
MX Mode and Function of Pins 24-31 of 8086 CPU Device.
Interrupt Acknowledge
Processor State
Read Memory
Write Memory
Read I/O Port
Write I/O Port
Code Access
Passive
-
MN/
Halt
MX = 1
-
MX = 1 (Min Mode)
HOLD
HLDA
M/
-
-
DT/R
-
ALE
INTA
DEN
WR
47
-
IO
column in Table 14. When the 8086 P operates in this
mode, it presents a control bus very similar to that of the
8085 P, and requires only an address latch and a clock
generator to form a CPU module.
request input; and INTR is the “maskable” interrupt
request input. If the 8086 P is operating in the “min”
mode, then the
available on Pin 24 (see Figure 20). However, if the
8086 P is operating in the “max” mode, then the
signal must be derived from the
the 8288 bus controller. Table 15 presents the processor
status and 8288 active outputs based on the
-
S2 “max” mode status signals.
-
INTA (Interrupt Acknowledge) pin is
8288 Active Output
MN/
XR88C681
-
MX = 0 (Max Mode)
-
-
-
-
-
MRDC
MRDC
MWTC
-
IOWC
-
None
None
IORC
INTA
S0,
-
-
RQ/
RQ/
-
-
LOCK
QS0
QS1
S0,
-
-
-
S2
S1
S0
-
S1, and
-
-
GT0
GT1
-
S1 and
-
S0,
-
S2 pins via
-
-
S2
S1, and
-
INTA