SC16C850SVIBS-S NXP Semiconductors, SC16C850SVIBS-S Datasheet - Page 17

• Manufacturer Part Number: SC16C850SVIBS-S
• Manufacturer: NXP Semiconductors

Specifications of SC16C850SVIBS-S

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Philips Semiconductors
9397 750 11618
Product data
6.6.2 Block DMA transfers (DMA mode 1)
6.7 Sleep mode
Figure 11
Transmitter:
available. It becomes inactive when the FIFO is full.
Receiver:
a time-out interrupt occurs. It will go inactive when the FIFO is empty or an error in
the RX FIFO is flagged by LSR[7].
Sleep mode is an enhanced feature of the SC16C754 UART. It is enabled when
EFR[4], the enhanced functions bit, is set and when IER[4] is set. Sleep mode is
entered when:
Remark: Sleep mode will not be entered if there is data in the RX FIFO.
In sleep mode, the UART clock and baud rate clock are stopped. Since most registers
are clocked using these clocks, the power consumption is greatly reduced. The UART
will wake up when any change is detected on the RX line, when there is any change
in the state of the modem input pins, or if data is written to the TX FIFO.
Remark: Writing to the divisor latches, DLL and DLH, to set the baud clock, must not
be done during sleep mode. Therefore, it is advisable to disable sleep mode using
IER[4] before writing to DLL or DLH.
•
•
•
Fig 11. TXRDY and RXRDY in DMA mode 1.
The serial data input line, RX, is idle (see
conditions”).
The TX FIFO and TX shift register are empty.
There are no interrupts pending except THR and time-out interrupts.
TRIGGER
LEVEL
wrptr
wrptr
shows TXRDY and RXRDY in DMA mode 1.
RXRDY becomes active when the trigger level has been reached, or when
TXRDY is active when there is a trigger level number of spaces
TX
Rev. 04 — 19 June 2003
FIFO FULL
TXRDY
TXRDY
Section 6.8 “Break and time-out
TRIGGER
LEVEL
rdptr
rdptr
Quad UART with 64-byte FIFO
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
FIFO EMPTY
RX
SC16C754
AT LEAST ONE
LOCATION FILLED
RXRDY
RXRDY
002aaa234
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