SC16C650BIA44 NXP Semiconductors, SC16C650BIA44 Datasheet - Page 11

• Manufacturer Part Number: SC16C650BIA44
• Manufacturer: NXP Semiconductors

Specifications of SC16C650BIA44

• Transmitter And Receiver Fifo Counter: Yes
• Package Type: PLCC
• Operating Supply Voltage (max): 5.5V
• Mounting: Surface Mount
• Pin Count: 44
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
SC16C650B_4
Product data sheet
6.5 Special feature software flow control
6.6 Hardware/software and time-out interrupts
In the event that the receive buffer is overfilling and flow control needs to be executed, the
SC16C650B automatically sends an Xoff message (when enabled) via the serial TX
output to the remote modem. The SC16C650B sends the Xoff1/Xoff2 characters as soon
as received data passes the programmed trigger level. To clear this condition, the
SC16C650B will transmit the programmed Xon1/Xon2 characters as soon as receive data
drops below the next low or programmed trigger level.
A special feature is provided to detect an 8-bit character when EFR[5] is set. When 8-bit
character is detected, it will be placed on the user-accessible data stack along with normal
incoming RX data. This condition is selected in conjunction with EFR[3:0]. Note that
software flow control should be turned off when using this special mode by setting
EFR[3:0] to a logic 0.
The SC16C650B compares each incoming receive character with Xoff2 data. If a match
exists, the received data will be transferred to the FIFO, and ISR[4] will be set to indicate
detection of a special character. Although
each X-register with eight bits of character information, the actual number of bits is
dependent on the programmed word length. Line Control Register bits LCR[1:0] define the
number of character bits, i.e., either 5 bits, 6 bits, 7 bits or 8 bits. The word length selected
by LCR[1:0] also determine the number of bits that will be used for the special character
comparison. Bit 0 in the X-registers corresponds with the LSB bit for the receive character.
Three special interrupts have been added to monitor the hardware and software flow
control. The interrupts are enabled by IER[7:5]. Care must be taken when handling these
interrupts. Following a reset, the transmitter interrupt is enabled, the SC16C650B will
issue an interrupt to indicate that the Transmit Holding Register is empty. This interrupt
must be serviced prior to continuing operations. The ISR register provides the current
singular highest priority interrupt only. It could be noted that CTS and RTS interrupts have
lowest interrupt priority. A condition can exist where a higher priority interrupt may mask
the lower priority CTS/RTS interrupt(s). Only after servicing the higher pending interrupt
will the lower priority CTS/RTS interrupt(s) be reflected in the status register. Servicing the
interrupt without investigating further interrupt conditions can result in data errors.
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time-Out have the same interrupt
priority (when enabled by IER[0]). The receiver issues an interrupt after the number of
characters have reached the programmed trigger level. In this case, the SC16C650B
FIFO may hold more characters than the programmed trigger level. Following the removal
of a data byte, the user should re-check LSR[0] for additional characters. A Receive
Time-Out will not occur if the receive FIFO is empty. The time-out counter is reset at the
center of each stop bit received or each time the Receive Holding Register (RHR) is read.
The actual time-out value is 4 character time.
Rev. 04 — 14 September 2009
UART with 32-byte FIFOs and IrDA encoder/decoder
Table 8 “SC16C650B internal registers”
SC16C650B
© NXP B.V. 2009. All rights reserved.
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