SC16C650BIA44 NXP Semiconductors, SC16C650BIA44 Datasheet - Page 7

• Manufacturer Part Number: SC16C650BIA44
• Manufacturer: NXP Semiconductors

Specifications of SC16C650BIA44

• Transmitter And Receiver Fifo Counter: Yes
• Package Type: PLCC
• Operating Supply Voltage (max): 5.5V
• Mounting: Surface Mount
• Pin Count: 44
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
Table 2.
SC16C650B_4
Product data sheet
Symbol
RESET
RI
RTS
RXRDY
RX
TX
TXRDY
V
GND
IOW
IOW
CC
Pin description
Pin
PLCC44 LQFP48 HVQFN32
39
43
36
32
11
13
27
44
22
21
20
35
41
32
29
7
8
23
42
18
17
16
…continued
24
-
21
19
5
6
15
27
13
-
11
[1]
Type
I
I
O
O
I
O
O
power
power
I
I
Rev. 04 — 14 September 2009
Description
Master Reset. When active (HIGH), MR clears most UART
registers and sets the levels of various output signals.
Ring indicator. RI is a modem status signal. Its condition can be
checked by reading MSR[6] (RI). MSR[2] ( RI) indicates that RI has
changed from a LOW to a HIGH level since the last read from the
MSR. If the modem status interrupt is enabled when this transition
occurs, an interrupt is generated.
Request to send. When active, RTS informs the modem or data
set that the UART is ready to receive data. RTS is set to the active
level by setting the RTS modem control register bit and is set to the
inactive (HIGH) level either as a result of a Master Reset or during
loopback mode operations or by clearing bit 1 (RTS) of the MCR. In
the auto-RTS mode, RTS is set to the inactive level by the receiver
threshold control logic.
Receiver ready. Receiver direct memory access (DMA) signaling is
available with RXRDY. When operating in the FIFO mode, one of
two types of DMA signaling can be selected using the FIFO Control
Register bit 3 (FCR[3]). When operating in the 16C450 mode, only
DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in
which a transfer is made between CPU bus cycles. Mode 1
supports multi-transfer DMA in which multiple transfers are made
continuously until the receiver FIFO has been emptied. In DMA
mode 0 (FCR[0] = 0 or FCR[0] = 1, FCR[3] = 0), when there is at
least one character in the receiver FIFO or Receive Holding
Register, RXRDY is active (LOW). When RXRDY has been active
but there are no characters in the FIFO or holding register, RXRDY
goes inactive (HIGH). In DMA mode 1 (FCR[0] = 1, FCR[3] = 1),
when the trigger level or the time-out has been reached, RXRDY
goes active (LOW); when it has been active but there are no more
characters in the FIFO or holding register, it goes inactive (HIGH).
Serial data input. RX is serial data input from a connected
communications device.
Serial data output. TX is composite serial data output to a
connected communication device. TX is set to the marking (HIGH)
level as a result of Master Reset.
Transmitter ready. Transmitter DMA signaling is available with
TXRDY. When operating in the FIFO mode, one of two types of
DMA signaling can be selected using FCR[3]. When operating in
the 16C450 mode, only DMA mode 0 is allowed. Mode 0 supports
single-transfer DMA in which a transfer is made between CPU bus
cycles. Mode 1 supports multi-transfer DMA in which multiple
transfers are made continuously until the transmit FIFO has been
filled.
2.5 V, 3 V or 5 V supply voltage.
Ground voltage.
Write inputs. When either IOW or IOW is active (LOW or HIGH,
respectively) and while the UART is selected, the CPU is allowed to
write control words or data into a selected UART register. Only one
of these inputs is required to transfer data during a write operation;
the other input should be tied to its inactive level (i.e., IOW tied LOW
or IOW tied HIGH).
UART with 32-byte FIFOs and IrDA encoder/decoder
SC16C650B
© NXP B.V. 2009. All rights reserved.
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