ISP1504A1ETTM STEricsson, ISP1504A1ETTM Datasheet
ISP1504A1ETTM
Specifications of ISP1504A1ETTM
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ISP1504A1ETTM Summary of contents
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ISP1504A1; ISP1504C1 ULPI Hi-Speed USB On-The-Go transceiver Rev. 04 — 20 May 2010 1. General description The ISP1504A1; ISP1504C1 (ISP1504x1 Universal Serial Bus (USB) On-The-Go (OTG) transceiver that is fully compliant with Universal Serial Bus Specification Rev. 2.0, ...
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Supports external charge pump Complete control over bus resistors Data line and V Integrated V Integrated cable (ID) detector Highly optimized ULPI-compliant interface 60 MHz, 12-bit interface between the core and the transceiver Integrated Phase-Locked Loop ...
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... Video camera 4. Ordering information Table 1. Ordering information Commercial Marking Crystal or clock product code frequency [1] ISP1504A1ETTM 504M 19.2 MHz [1] ISP1504C1ETTM 504P 26 MHz [1] The package marking is the first line of text on the IC package and can be used for IC identification. CD00222688 Product data sheet ISP1504A1; ISP1504C1 ...
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Block diagram A4 CLOCK B1, A1, A2, A3, A5, A6, 8 DATA B6, C6 [7:0] ULPI interface E5 DIR D6 STP D5 NXT C3 CS_N/PWRDN C4 RESET_N global clocks F5 XTAL1 F6 XTAL2 B2, B3, B5 interface voltage V ...
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Pinning information 6.1 Pinning Fig 2. Pin configuration TFBGA36; top view 6.2 Pin description Table 2. Pin description [1][2] [3] Symbol Pin Type DATA1 A1 I/O DATA2 A2 I/O DATA3 A3 I/O CLOCK A4 O DATA4 A5 I/O DATA5 ...
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Table 2. Pin description …continued [1][2] [3] Symbol Pin Type CS_N PWRDN RESET_N C4 I DATA7 PSW_N D4 OD NXT D5 O STP D6 I FAULT E2 I REG3V3 E3 ...
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Functional description 7.1 ULPI interface controller The ISP1504x1 provides a 12-pin interface that is compliant with UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1. This interface must be connected to the USB link. The ULPI interface controller provides the ...
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Differential and single-ended receivers to receive data at high-speed, full-speed and low-speed • Squelch circuit to detect high-speed bus activity • High-speed disconnect detector 45 Ω high-speed bus terminations on DP and DM • • 1.5 kΩ pull-up resistor ...
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The ID detector to sense the ID pin of the micro-USB cable. The ID pin dictates which device is initially configured as the host and which as the peripheral. • V comparators to determine the V BUS detection, SRP ...
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Band gap reference voltage The band gap circuit provides a stable internal voltage reference to bias analog circuitry. The band gap requires an accurate external reference resistor. Connect a 12 kΩ ± resistor between the RREF pin ...
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DP and DM DP (data plus) and DM (data minus) are USB differential data pins. These must be connected to the D+ and D− pins of the USB receptacle. 7.9.5 FAULT If an external V circuit can be connected ...
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Table 3. Application OTG Standard host Standard peripheral Fig 3. Application circuit components 7.9.10 REG3V3 and REG1V8 Regulator output voltage. These supplies are used to power the ISP1504x1 internal digital and analog circuits, and must not be used to power ...
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DIR ULPI direction output pin. Controls the direction of the data bus. By default, the ISP1504x1 holds DIR at LOW, causing the data bus input. When DIR is LOW, the ISP1504x1 listens for data from the ...
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Modes of operation 8.1 ULPI modes The ISP1504x1 ULPI bus can be programmed to operate in five modes. Each mode reconfigures the signals on the data bus as described in the following subsections. Setting more than one mode will ...
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Table 4. Signal name DIR STP NXT 8.1.2 Low-power mode When the USB is idle, the link can place the ISP1504x1 into low-power mode (also called suspend mode). In low-power mode, the data bus definition changes to that shown in ...
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Table 5. Signal mapping during low-power mode Signal Maps to LINESTATE0 DATA0 LINESTATE1 DATA1 Reserved DATA2 INT DATA3 8.1.3 6-pin full-speed or low-speed serial mode If the link requires a 6-pin serial interface to transmit and receive full-speed or low-speed ...
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Table 7. Signal mapping for 3-pin serial mode Signal Maps to TX_ENABLE DATA0 DAT DATA1 SE0 DATA2 INT DATA3 Reserved DATA[7:4] 8.1.5 Power-down mode In this mode, the PHY will 3-state the DATA[7:0], CLOCK, NXT and DIR pins. The link ...
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CS_N/PWRDN CLOCK DATA[7:0] DIR NXT STP Fig 4. Entering and exiting 3-state in normal mode 8.2 USB state transitions A Hi-Speed USB host or an OTG device handles more than one electrical state as defined in Universal ...
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Table 8. Operating states and corresponding resistor settings Signaling mode Register settings XCVR TERM SELECT SELECT [1:0] General settings 3-state drivers XXb Xb Power < 01b 0b BUS V B_SESS_END Host settings Host chirp 00b 0b Host ...
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Table 8. Operating states and corresponding resistor settings Signaling mode Register settings XCVR TERM SELECT SELECT [1:0] OTG device 01b 1b peripheral high-speed and full-speed suspend OTG device 01b 1b peripheral high-speed and full-speed resume OTG device 00b 0b peripheral ...
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Protocol description This following subsections describe the protocol for using the ISP1504x1. 9.1 ULPI references The ISP1504x1 provides a 12-pin ULPI interface to communicate with the link highly recommended that you read UTMI+ Low Pin Interface (ULPI) ...
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The recommended power-up sequence for the link is: 1. The CS_N/PWRDN pin transitions from HIGH to LOW. 2. The link waits for t 3. The link may start to detect DIR status level. If DIR is detected LOW for three ...
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CC(I/O) CS_N/ PWRDN REG1V8 t POR internal t REGUP POR XTAL1 CLOCK DATA[7:0] DIR STP NXT applied to the ISP1504x1 turned on. ULPI interface ...
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Interface protection By default, the ISP1504x1 enables a weak pull-up resistor on STP. If the STP pin is unexpectedly HIGH at any time, the ISP1504x1 will protect the ULPI interface by enabling weak pull-down resistors on DATA[7:0]. The interface ...
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CLOCK CS_N/PWRDN DATA[7:0] Hi-Z (input) DIR Hi-Z (input) STP NXT Fig 8. Interface behavior with respect to CS_N/PWRDN 9.4 V power and overcurrent detection BUS 9.4.1 Driving The ISP1504x1 supports external 5 V supplies. The ISP1504x1 ...
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TXCMD By default, the link must drive the ULPI bus to its idle state of 00h. To send commands and USB packets, the link drives a nonzero value on DATA[7:0] to the ISP1504x1 by sending a byte called TXCMD. ...
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Table 11. RXCMD byte format DATA Name Description and value LINESTATE LINESTATE signals: For a definition of LINESTATE, see DATA0 — LINESTATE[0] DATA1 — LINESTATE[ state Encoded V BUS BUS ...
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Table 13. LINESTATE[1:0] encoding for downstream facing ports: host DP_PULLDOWN and DM_PULLDOWN = 1. Mode Low-speed XCVRSELECT[1:0] 10 TERMSELECT 1 OPMODE[1:0] X LINESTATE[1:0] 00 SE0 01 LS-K 10 LS-J 11 SE1 [1] !squelch indicates inactive squelch. !HS_Differential_Receiver_Output indicates inactive HS_Differential_Receiver_Output. ...
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USE_EXT_VBUS_IND, IND_PASSTHRU Fig 10. RXCMD A_VBUS_VLD indicator source 9.5.2.3 Using and selecting the V The V BUS link whenever there is a change in the V must first enable corresponding interrupts in the USB Interrupt Enable Rising Edge and USB ...
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OTG devices: provide a minimum then there is no need for an overcurrent detection circuit because the internal A_VBUS_VLD comparator is sufficient. If the OTG A-device provides more than 100 ...
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Register read and write operations Figure 11 addressing and extended addressing register operations. Extended register addressing is optional for links. Note that register operations will be aborted if the ISP1504x1 asserts DIR during the operation. When a register operation ...
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T up its clock within 5.6 ms, leaving 200 μs for the link to start transmitting the Chirp K, and 1.2 ms for the Chirp K to complete (worst case with 10 % slow ...
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USB reset T 0 TXCMD (REGW) SE0 DATA [ 7:0 ] DIR STP NXT 01 (FS) XCVR SELECT TERM SELECT 00 (normal) OP MODE J (01b) SE0 (00b) LINE STATE TXCMD SE0 (REGW) DATA [ 7:0 ] DIR STP NXT ...
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USB packet transmit and receive An example of a packet transmit and receive is shown in packets, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1. link sends TXCMD CLOCK TXCMD DATA [ 7:0 ] DIR STP NXT ...
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Allowed link decision time The amount of clock cycles allocated to the link to respond to a received packet and correctly receive back-to-back packets is given in values given in packet sequences and timing are shown in UTMI+ Low ...
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DP or DATA DM CLOCK D D N−1 N DATA [7:0] DIR STP NXT TX end delay (two to five clocks) Fig 14. High-speed transmit-to-transmit packet timing DP or EOP DATA DM CLOCK N−4 N−2 DATA ...
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ISP1504x1 operates just as in full-speed mode, and sends all data with full-speed rise and fall times. Whenever the link transmits a USB packet in preamble mode, the ISP1504x1 will automatically send a preamble header at full-speed bit rate before ...
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Resume K: When the host wants to wake up the peripheral, it sets OPMODE[1:0] to 10b and transmits a K for at least 20 ms. The peripheral link sees the resume K on LINESTATE, and asserts STP to wake ...
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DATA [ 7:0 ] DIR STP NXT OPMODE 00b LINE J STATE CLOCK TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT OPMODE SUSPEND M LINE J STATE DP DM Timing is not to scale. Fig 17. Full-speed suspend ...
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The sequence of events related to a host and a peripheral, both with ISP1504x1 follows. 1. High-speed idle: Initially, the host and the peripheral are idle. The host has its 15 kΩ pull-down resistors enabled (DP_PULLDOWN and DM_PULLDOWN ...
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HS idle TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT XCVR 00b SELECT TERM SELECT OP 00b MODE !SQUELCH SQUELCH (01b) (00b) LINE STATE CLOCK TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT XCVR 00b SELECT TERM SELECT ...
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Remote wake-up The ISP1504x1 supports peripherals that initiate remote wake-up resume. When placed into USB suspend, the peripheral link remembers what speed it was originally operating. Depending on the original speed, the link follows one of the protocols detailed ...
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LINESTATE DATA [ 7:0 ] DIR STP NXT XCVR SELECT TERM SELECT OP MODE TXCMD LINESTATE REGW DATA [ 7:0 ] DIR STP NXT XCVR SELECT TERM SELECT OP MODE Timing is not to scale. Fig 19. Remote wake-up from ...
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PHY will not transmit any EOP. The ISP1504x1 will also detect if the PID byte is A5h, indicating an SOF packet and automatically send a long EOP when STP is asserted. To transmit chirp and resume signaling, the link must ...
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OTG comparators The ISP1504x1 provides comparators that conform to On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3 requirements of V and V B_SESS_END V A_SESS_VLD are communicated to the link by RXCMDs as described in comparators is described ...
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SYNC DATA0 (TX_ENABLE) DATA1 (TX_DAT) DATA2 (TX_SE0) DATA4 (RX_DP) DATA5 (RX_DM) DATA6 (RX_RCV Fig 21. Example of transmit followed by receive in 6-pin serial mode SYNC DATA0 (TX_ENABLE) DATA1 (TX_DAT/ RX_RCV) DATA2 (TX_SE0/ RX_SE0 Fig 22. ...
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Aborting transfers The ISP1504x1 supports aborting transfers on the ULPI bus. For details, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1, Section 3.8.4. 9.15 Avoiding contention on the ULPI data bus Because the ULPI data bus is ...
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Register map Table 19. Immediate register set overview Field name Vendor ID Low register Vendor ID High register Product ID Low register Product ID High register Function Control register Interface Control register OTG Control register USB Interrupt Enable Rising ...
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Immediate register set 10.1.1 Vendor ID and Product ID registers 10.1.1.1 Vendor ID Low register Table 21 shows the bit description of the register. Table 21. Vendor ID Low register (address R = 00h) bit description Legend: * reset ...
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Table 26. Function Control register (address R = 04h to 06h 04h 05h 06h) bit description Bit Symbol Description 7 - reserved 6 SUSPENDM Suspend LOW: Active LOW PHY suspend. Sets the PHY into ...
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Table 28. Interface Control register (address R = 07h to 09h 07h 08h 09h) bit description Bit Symbol Description 7 INTF_PROT_DIS Interface Protect Disable: Controls circuitry built into the ISP1504x1 to protect the ULPI ...
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Table 30. OTG Control register (address R = 0Ah to 0Ch 0Ah 0Bh 0Ch) bit description Bit Symbol Description 7 USE_EXT_VBUS Use External V _IND 0b — Use the internal OTG comparator. 1b — ...
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Table 32. USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh 0Dh 0Eh 0Fh) bit description Bit Symbol Description reserved 4 ID_GND_R ID Ground Rise: Enables interrupts ...
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Table 35. USB Interrupt Status register (address R = 13h) bit allocation Bit 7 6 Symbol reserved Reset X X Access R R Table 36. USB Interrupt Status register (address R = 13h) bit description Bit Symbol Description 7 to ...
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Debug register The bit allocation of the Debug register is given in current value of signals useful for debugging. Table 39. Debug register (address R = 15h) bit allocation Bit 7 6 Symbol Reset 0 0 Access R R ...
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Table 43. Power Control register (address R = 3Dh to 3Fh 3Dh 3Eh 3Fh) bit description Bit Symbol Description reserved; the link must never write logic 1 to these bits. ...
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Limiting values Table 44. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC V input/output supply voltage CC(I/O) V input voltage I V electrostatic discharge ESD voltage I latch-up current ...
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Static characteristics Table 46. Static characteristics: supply pins CC(I/O) Typical values are 3 CC(I/O) Symbol Parameter V ...
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Table 47. Static characteristics: digital pins CLOCK, DIR, STP, NXT, DATA[7:0], RESET_N, CS_N/PWRDN CC(I/O) Typical values are 3 ...
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Table 50. Static characteristics: analog I/O pins CC(I/O) Typical values are 3 CC(I/O) Symbol Parameter V ...
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Table 51. Static characteristics: analog pin CC(I/O) Typical values are 3 CC(I/O) Symbol Parameter Comparators V A-device ...
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Dynamic characteristics Table 54. Dynamic characteristics: reset and clock CC(I/O) Typical values are 3 CC(I/O) Symbol Parameter ...
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Table 55. Dynamic characteristics: digital I/O pins CC(I/O) Typical values are 3 CC(I/O) Symbol Parameter V = 1.65 ...
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Table 57. Dynamic characteristics: analog I/O pins DP and CC(I/O) Typical values are 3 CC(I/O) Symbol Parameter ...
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Table 57. Dynamic characteristics: analog I/O pins DP and CC(I/O) Typical values are 3 CC(I/O) Symbol Parameter ...
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CLOCK CONTROL IN (STP) DATA IN (8-BIT) CONTROL OUT (DIR, NXT) DATA OUT (8-BIT) Fig 27. ULPI timing interface Fig 28. Bus turnaround timing CD00222688 Product data sheet ISP1504A1; ISP1504C1 t t su(STP) h(STP su(DATA) h(DATA ...
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Application information Table 58. Recommended list of materials Designator Application C highly recommended for all bypass applications C highly recommended for all filter applications C mandatory for peripherals VBUS mandatory for host mandatory for OTG R recommended; for applications ...
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V BUS 2 D− 3 USB D+ STANDARD-B 4 GND RECEPTACLE C VBUS C bypass Fig 29. Using the ISP1504x1 with a standard USB Peripheral Controller; external crystal ...
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V IN FAULT V BUS R pullup SWITCH ON OUT 1 V BUS 2 D− USB MICRO- RECEPTACLE 5 GND C VBUS (1) Can be a square ...
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V IN FAULT V BUS R pullup SWITCH ON OUT 1 V BUS 2 D− 3 USB D+ STANDARD-A 4 GND RECEPTACLE C VBUS Fig 31. Using the ISP1504x1 with a ...
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Package outline TFBGA36: plastic thin fine-pitch ball grid array package; 36 balls; body 3.5 x 3.5 x 0.8 mm ball A1 index area 1 ball index area DIMENSIONS ...
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Abbreviations Table 59. Acronym ASIC ATX EOP ESR FS HBM HNP NRZI OTG PHY PID PLL POR RXCMD SE0 SOF SRP SYNC TTL TXCMD USB USB-IF ULPI UTMI UTMI+ [1] Physical layer containing the USB ...
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Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) (JESD22-A114D) [7] Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM) (JESD22-A115-A) [8] Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components (JESD22-C101-C) 19. Revision history Table 60. Revision ...
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Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 2. Pin description . . . . . . . . . ...
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Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Fig 2. Pin configuration TFBGA36; top ...
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Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . ...
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Vendor ID and Product ID registers . . . . . . . . 49 10.1.1.1 Vendor ID Low register . . . . . . . . . . . . . . . . . . 49 ...
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... Please Read Carefully: STMicroelectronics NV or Telefonaktiebolaget LM Ericsson. All other names are the property of their respective owners. © ST-Ericsson, 2010 - All rights reserved Contact information at www.stericsson.com under Contacts www.stericsson.com Rev. 04 — 20 May 2010 ULPI HS USB OTG transceiver © ST-ERICSSON 2010. All rights reserved. ...